SG11201508467SA - Method and apparatus for through-silicon vias reveal - Google Patents

Method and apparatus for through-silicon vias reveal

Info

Publication number
SG11201508467SA
SG11201508467SA SG11201508467SA SG11201508467SA SG11201508467SA SG 11201508467S A SG11201508467S A SG 11201508467SA SG 11201508467S A SG11201508467S A SG 11201508467SA SG 11201508467S A SG11201508467S A SG 11201508467SA SG 11201508467S A SG11201508467S A SG 11201508467SA
Authority
SG
Singapore
Prior art keywords
reveal
silicon vias
vias
silicon
vias reveal
Prior art date
Application number
SG11201508467SA
Other languages
English (en)
Inventor
Hui Wang
Fuping Chen
Xiaoyan Zhang
Original Assignee
Acm Res Shanghai Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Acm Res Shanghai Inc filed Critical Acm Res Shanghai Inc
Publication of SG11201508467SA publication Critical patent/SG11201508467SA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67075—Apparatus for fluid treatment for etching for wet etching
    • H01L21/6708—Apparatus for fluid treatment for etching for wet etching using mainly spraying means, e.g. nozzles

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Weting (AREA)
SG11201508467SA 2013-04-22 2013-04-22 Method and apparatus for through-silicon vias reveal SG11201508467SA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2013/074524 WO2014172835A1 (en) 2013-04-22 2013-04-22 Method and apparatus for through-silicon vias reveal

Publications (1)

Publication Number Publication Date
SG11201508467SA true SG11201508467SA (en) 2015-11-27

Family

ID=51790968

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201508467SA SG11201508467SA (en) 2013-04-22 2013-04-22 Method and apparatus for through-silicon vias reveal

Country Status (4)

Country Link
KR (1) KR102024122B1 (ko)
CN (1) CN105122440B (ko)
SG (1) SG11201508467SA (ko)
WO (1) WO2014172835A1 (ko)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9870928B2 (en) 2014-10-31 2018-01-16 Veeco Precision Surface Processing Llc System and method for updating an arm scan profile through a graphical user interface
WO2016070036A1 (en) * 2014-10-31 2016-05-06 Veeco Precision Surface Processing Llc A system and method for performing a wet etching process
AT518466A3 (de) * 2014-10-31 2019-07-15 Veeco Precision Surface Proc Llc System und Verfahren zum Ausführen eines Nass-Ätzprozesses
TWI738757B (zh) 2016-04-05 2021-09-11 美商維克儀器公司 經由化學的適應性峰化來控制蝕刻速率的裝置和方法
WO2017173613A1 (en) * 2016-04-07 2017-10-12 Acm Research (Shanghai) Inc. Tsv structure planarization process and apparatus
WO2018160461A1 (en) 2017-03-03 2018-09-07 Veeco Precision Surface Processing Llc An apparatus and method for wafer thinning in advanced packaging applications
US10957625B2 (en) 2017-12-29 2021-03-23 Micron Technology, Inc. Pillar-last methods for forming semiconductor devices

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3972846B2 (ja) * 2003-03-25 2007-09-05 セイコーエプソン株式会社 半導体装置の製造方法
JP2005191170A (ja) * 2003-12-25 2005-07-14 Seiko Epson Corp 半導体装置の製造方法、半導体装置の製造装置、半導体装置、回路基板および電子機器
FR2886053B1 (fr) * 2005-05-19 2007-08-10 Soitec Silicon On Insulator Procede de gravure chimique uniforme
KR20100050403A (ko) * 2008-11-04 2010-05-13 주식회사 실트론 대상물의 습식 처리 장치 및 방법과 이에 사용되는 유체 확산판
US8501587B2 (en) * 2009-01-13 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated chips and methods of fabrication thereof
US8264066B2 (en) * 2009-07-08 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Liner formation in 3DIC structures
US8596623B2 (en) * 2009-12-18 2013-12-03 Lam Research Ag Device and process for liquid treatment of a wafer shaped article
CN102403270B (zh) * 2011-12-07 2013-09-18 南通富士通微电子股份有限公司 硅通孔互连结构的形成方法

Also Published As

Publication number Publication date
KR102024122B1 (ko) 2019-09-23
CN105122440B (zh) 2019-03-29
KR20150145258A (ko) 2015-12-29
CN105122440A (zh) 2015-12-02
WO2014172835A1 (en) 2014-10-30

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