SG11201404307TA - Fully molded fan-out - Google Patents

Fully molded fan-out

Info

Publication number
SG11201404307TA
SG11201404307TA SG11201404307TA SG11201404307TA SG11201404307TA SG 11201404307T A SG11201404307T A SG 11201404307TA SG 11201404307T A SG11201404307T A SG 11201404307TA SG 11201404307T A SG11201404307T A SG 11201404307TA SG 11201404307T A SG11201404307T A SG 11201404307TA
Authority
SG
Singapore
Prior art keywords
fully molded
molded fan
fan
fully
molded
Prior art date
Application number
SG11201404307TA
Inventor
Christopher Scanlan
Original Assignee
Deca Technologies Inc
Christopher Scanlan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deca Technologies Inc, Christopher Scanlan filed Critical Deca Technologies Inc
Publication of SG11201404307TA publication Critical patent/SG11201404307TA/en

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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L2224/13001—Core members of the bump connector
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    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/2101—Structure
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
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    • H—ELECTRICITY
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
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    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Moulds For Moulding Plastics Or The Like (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)
SG11201404307TA 2011-12-30 2012-12-28 Fully molded fan-out SG11201404307TA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/341,654 US8604600B2 (en) 2011-12-30 2011-12-30 Fully molded fan-out
PCT/US2012/072164 WO2013102137A2 (en) 2011-12-30 2012-12-28 Fully molded fan-out

Publications (1)

Publication Number Publication Date
SG11201404307TA true SG11201404307TA (en) 2014-10-30

Family

ID=48678422

Family Applications (2)

Application Number Title Priority Date Filing Date
SG11201404307TA SG11201404307TA (en) 2011-12-30 2012-12-28 Fully molded fan-out
SG11201404309VA SG11201404309VA (en) 2011-12-30 2012-12-28 Die up fully molded fan-out wafer level packaging

Family Applications After (1)

Application Number Title Priority Date Filing Date
SG11201404309VA SG11201404309VA (en) 2011-12-30 2012-12-28 Die up fully molded fan-out wafer level packaging

Country Status (4)

Country Link
US (2) US8604600B2 (en)
CN (2) CN103187322B (en)
SG (2) SG11201404307TA (en)
WO (1) WO2013102137A2 (en)

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