CN113380641A

CN113380641A - Manufacturing method of crystal grain packaging structure

Info

Publication number: CN113380641A
Application number: CN202010116689.XA
Authority: CN
Inventors: 赖建志; 林泓彣
Original assignee: Comchip Technology Corp
Current assignee: Comchip Technology Corp; Comchip Technology Co Ltd
Priority date: 2020-02-25
Filing date: 2020-02-25
Publication date: 2021-09-10

Abstract

The invention discloses a manufacturing method of a crystal grain packaging structure, which comprises the following operations. A conductive substrate having a plurality of grooves is provided. A die is disposed in each recess. Forming a conductive layer covering the die and the conductive substrate. Forming a patterned photoresist layer on the conductive layer, wherein the patterned photoresist layer has a plurality of openings exposing a plurality of regions of the conductive layer. A shield is formed over regions of the conductive layer. After the mask is formed, the patterned photoresist layer is removed. And selectively etching the conductive layer and the conductive substrate below the conductive layer to a predetermined depth by using the mask to form a plurality of conductive bumps and a plurality of electrodes, wherein the remaining conductive substrate comprises a bottom plate, the electrodes are positioned on the bottom plate, and the conductive bumps are positioned on the dies. And forming an upper sealing adhesive layer to cover the bottom plate and the crystal grains, wherein the shielding, the conductive bumps or the electrodes are exposed out of the upper sealing adhesive layer. The invention can achieve the miniaturization of the crystal grain packaging structure in the vertical direction and improve the heat dissipation effect of the power chip.

Description

Manufacturing method of crystal grain packaging structure

Technical Field

The present invention relates to a method for manufacturing a package structure, and more particularly, to a method for manufacturing an embedded die package structure.

Background

With the popularity of consumer electronics, for example: the demands of consumers for high functionality and small size of electronic products are becoming more and more obvious for mobile phones, tablet computers, pen phones, and the like. The chip packaging process is an important step in the process of forming electronic products. To reduce the size of the chip package and further improve the performance of the chip package, it is an important issue.

The conventional packaging process is to package the semiconductor dies cut from the wafer one by one, and the process includes Wire Bonding (Wire Bonding) and Molding (Molding) besides Die Bonding (Die Bonding), which is time-consuming and labor-consuming. Furthermore, in the conventional method, the power chips in the power module are electrically connected by bonding wires, and the heat generated by the power chips is not easily dissipated.

Disclosure of Invention

The present invention is directed to overcoming the drawbacks of the prior art, and provides a method for manufacturing a die package structure to reduce the size of a chip package and improve the heat dissipation effect of a power chip.

According to some embodiments of the present invention, there is provided a method for manufacturing a die package, comprising the operations of: providing a conductive substrate with a plurality of grooves; crystal grains are arranged in each groove; forming a conductive layer covering the plurality of crystal grains and the conductive substrate; forming a patterned photoresist layer on the conductive layer, wherein the patterned photoresist layer is provided with a plurality of openings to expose a plurality of areas of the conductive layer; forming a shield on each region of the conductive layer; removing the patterned photoresist layer after forming the plurality of masks; selectively etching the conductive layer and the conductive substrate thereunder to a predetermined depth by using the plurality of masks to form a plurality of conductive bumps and a plurality of electrodes, wherein the remaining conductive substrate comprises a bottom plate, the plurality of electrodes are positioned on the bottom plate, and the plurality of conductive bumps are positioned on the plurality of crystal grains; and forming an upper sealing adhesive layer to cover the bottom plate and the plurality of crystal grains, wherein the plurality of shields, the plurality of conductive bumps or the plurality of electrodes are exposed out of the upper sealing adhesive layer.

In one embodiment, the conductive substrate is comprised of copper.

In one embodiment, the conductive substrate has a first thickness and each of the grooves has a depth in a range of 45% to 55% of the first thickness.

In one embodiment, each shield comprises a nickel layer and a gold layer disposed on the nickel layer.

In an embodiment, the method for manufacturing a die package structure further includes: after the upper sealing adhesive layer is formed, thinning the bottom plate to form a thinned bottom layer; and patterning the thinned bottom layer to form a circuit layer.

In an embodiment, the method for manufacturing a die package structure further includes: after the circuit layer is formed, forming a lower sealing glue layer to cover the circuit layer; and cutting the upper sealing adhesive layer and the lower sealing adhesive layer to obtain a plurality of packaging structures separated from each other.

In one embodiment, the thickness of each package structure is in a range of 130um to 200 um.

In one embodiment, forming the conductive layer comprises: forming a copper seed layer using electroless plating; and forming a copper plating layer on the copper seed layer using electroplating.

In one embodiment, forming an upper encapsulant layer covering the bottom plate and the plurality of dies comprises: forming a sealant material layer to cover the bottom plate, the plurality of crystal grains, the plurality of shields, the plurality of electrodes and the plurality of conductive bumps; and thinning the sealant material layer to expose the shields to the thinned sealant material layer.

In one embodiment, forming an upper encapsulant layer covering the bottom plate and the plurality of dies comprises: forming a sealant material layer to cover the bottom plate, the plurality of crystal grains, the plurality of shields, the plurality of electrodes and the plurality of conductive bumps; thinning the molding compound layer, wherein the plurality of shields are removed, so that the plurality of conductive bumps and the plurality of electrodes are exposed out of the thinned molding compound layer; and forming metal pads on the exposed conductive bumps and electrodes.

Compared with the prior art, the invention has obvious advantages and beneficial effects. By the technical scheme, the manufacturing method of the chip packaging structure of the invention omits a Wire bond (Wire bond) process in the traditional manufacturing method, has less selection limitation on an etching process and can simplify the manufacturing process of the chip packaging structure. Furthermore, the invention comprises a manufacturing method of the embedded type crystal grain packaging structure, which can achieve the miniaturization of the crystal grain packaging structure in the vertical direction and improve the heat dissipation effect of the power chip.

The above description will be described in detail by embodiments, and further explanation will be provided for the technical solution of the present invention.

Drawings

Aspects of the present invention will be better understood from the following description and drawings. It should be noted that many features are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of many of the features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A to 1B are flow charts illustrating methods for manufacturing package structures according to various embodiments of the present invention.

Fig. 2 to 14 are schematic cross-sectional views of manufacturing methods of package structures at different stages of manufacturing processes according to various embodiments of the invention.

[ notation ] to show

10: conductive substrate

10': base plate

10": thinned substrate

12: adhesive glue

20: groove

22: die

24: region(s)

26: electrode for electrochemical cell

28: conductive bump

30: copper seed layer

31: conductive layer

32: copper plating layer

34: the photoresist layer

35: shielding

36: upper adhesive tape layer

37: sealing compound material layer

38: lower adhesive tape

40: metal pad

50: line layer

300: packaging structure

A: region(s)

H1: thickness of

H2: depth of field

H3: thickness of

H4: thickness of

H5: thickness of

Detailed Description

In order to make the description of the embodiments of the present invention more thorough and complete, the following description is given for illustrative purposes with respect to the implementation aspects and specific examples of the present invention; it is not intended to be the only form in which the embodiments of the invention may be practiced or utilized. The various embodiments disclosed below may be combined with or substituted for one another where appropriate, and additional embodiments may be added to one embodiment without further recitation or description.

In the following description, numerous specific details are set forth to provide a thorough understanding of the following embodiments. However, embodiments of the invention may be practiced without these specific details. In other instances, well-known structures and devices are shown schematically in order to simplify the drawing.

In the embodiments and claims, the terms "a" and "an" can refer broadly to the singular or the plural unless the context specifically states otherwise. As used herein, the term "about" or "approximately" generally refers to a numerical value having an error or range of about twenty percent, preferably about ten percent, and more preferably about five percent.

An embodiment of the present invention provides a method for manufacturing an embedded die package, which can simplify the conventional process and reduce the heat dissipation problem of the package. Fig. 1A to 1B are flow charts illustrating a method 100 for manufacturing a package structure according to an embodiment of the invention. Fig. 2 to 14 are schematic cross-sectional views of the manufacturing method 100 of the package structure at various stages of the manufacturing process. As shown in fig. 1A and 1B, the method 100 includes steps S200, S202, S204, S206, S208, S210, S212, S214, S216, S218, S220, S222, and S224.

Referring to step S200, as shown in fig. 2, the conductive substrate 10 is provided or received. The conductive substrate 10 is made of a conductive material, for example: metal, graphene, or semiconductor material. In some embodiments, the conductive substrate 10 is made substantially of copper. In some embodiments, the thickness H1 of the conductive substrate 10 is about 2 times the thickness of the die (shown in fig. 4) to be packaged. For example, the thickness of the grains is about 100um and the thickness of the conductive substrate is about 200 um.

Referring to step S202, as shown in fig. 3, a plurality of grooves 20 are formed on the conductive substrate 10. For example, a photoresist layer is formed on the conductive substrate 10, and a plurality of openings are formed on the photoresist layer by a photolithography process. Then, the opening pattern is transferred to the conductive substrate 10 by an etching process. The plurality of grooves 20 are formed each having a depth H2. In some embodiments, the depth H2 is approximately in the range of 45% -55%, such as 50%, of the thickness H1. In some embodiments, the etching process may comprise dry or wet etching. In some embodiments, the photoresist layer is a Dry Film Resist (DFR).

Referring to step S204, as shown in fig. 4, a crystal grain 22 is provided in each recess 20. Die 22 may include, but is not limited to, Dynamic Random Access Memory (DRAM) devices, flash memory devices, solid State Random Access Memory (SRAM) devices, passive devices, frequency modulation module (radio frequency module) devices, other suitable devices, or a combination of the foregoing.

In some embodiments, the Die 22 may be secured within the recess 20 by a Die bonding process. Specifically, the adhesive 12 is first placed in each recess 20 of the conductive substrate 10, and then the die 22 is placed in each recess 20. Each die 22 is attached to the bottom of each recess 20 by adhesive 12, and the sidewall of each die 22 substantially touches or partially touches the sidewall of each recess 20. The top surface of each die 22 is substantially slightly lower, slightly higher or level than the upper surface of the conductive substrate 10. Then, the conductive substrate 10 may be selectively heated to accelerate the adhesion reaction. In some embodiments, one die is disposed in each recess 2022. In some embodiments, each die has a chip (Single chip). In another embodiment, each die has two chips (Dual chips). In some embodiments, the area of the groove is about 0.1x0.16mm²。

Referring to step S206, as shown in fig. 5, the conductive layer 31 is formed on the conductor substrate 10. In some embodiments, the conductive layer 31 includes a copper seed layer 30 and a copper electroplating layer 32 on the copper seed layer 30. In detail, after forming the copper seed layer 30 to cover the die 22 and the conductive substrate 10, the copper electroplating layer 32 is formed on the copper seed layer 30. For example, a copper seed layer 30 is formed on the conductive substrate 10 by electroless copper plating, and a copper plating layer 32 is formed on the copper seed layer 30 by electroplating. In some embodiments, the copper seed layer is about 10um to 100um thick. In some embodiments, the thickness of the copper plating layer is about 10 to 100 um.

With continued reference to fig. 5, after the conductive layer 31 is formed, a planarization process may optionally be performed on the conductive layer 31 to form a substantially planar surface. In some embodiments, the planarization process may include a Mechanical polishing (grinding) process, a Chemical Mechanical Polishing (CMP), one or more other applicable processes, or a combination thereof.

Referring to step S208, as shown in fig. 6A, a patterned photoresist layer 34 is formed over the conductive layer 31, wherein the patterned photoresist layer 34 has a plurality of openings exposing the plurality of regions 24 of the conductive layer 31. In some embodiments, the photoresist layer is a Dry Film Resist (DFR).

Continuing to step S210, referring to fig. 6B, a mask 35 is formed on each region 24 of the photoresist layer 34 as an etch-resistant material layer for the subsequent steps. The mask 35 is formed by an electroplating (electroplating) process, an electroless plating (electroplating) process, or other suitable methods. In some embodiments, the mask 35 is made of a material that is etch selective to copper. In some embodiments, the shield 35 is made of a solderable tin material. In some embodiments, the shield 35 comprises a nickel layer and a gold layer on the nickel layer.

Continuing to step S212, referring to fig. 6C, after forming the mask 35, the patterned photoresist layer 34 is removed, thereby leaving the mask 35 overlying each of the regions 24. In some embodiments, photoresist layer 34 is removed using a photoresist stripper or ashing (Ash).

In step S214, as shown in fig. 7, the conductive layer 31 and the conductive substrate 10 thereunder are selectively etched to a predetermined depth by using the mask 35 as an etching-resistant material layer to form a plurality of conductive bumps 28 and a plurality of electrodes 26. The remaining conductive substrate includes a backplane 10 'with electrodes 26 formed on the backplane 10' and conductive bumps 28 on the dies 22. In some embodiments, the conductive layer 31 and the conductive substrate 10 are etched using a wet etching method. In some embodiments, the predetermined depth is substantially equal to the depth of each groove 20. In some embodiments, the thickness H3 of the base plate 10' is substantially equal to or thicker than the thickness of the die.

Step S216 is continued, refer to fig. 8A to 8C. As shown in fig. 8A, a molding compound material layer 37 is formed to cover the bottom plate 10', the die 22, the shield 35, the electrode 26 and the conductive bump 28. Then, as shown in fig. 8B, the encapsulant layer 37 is thinned by, for example, grinding, to form an upper encapsulant layer 36, wherein the mask 35, the electrode 26, or the conductive bump 28 exposes the upper encapsulant layer 36. In detail, in an embodiment of the present invention, as shown in fig. 8B, after the thinning process is performed, the mask 35 is exposed to the thinned molding compound layer 37, and the mask 35 is remained. In another embodiment of the present invention, as shown in fig. 8C, after the thinning process, the mask 35 is removed, such that the conductive bump 28 and the conductive layer 31 of the electrode 26 are exposed from the upper encapsulant layer 36.

In some embodiments, examples of the formation of the molding compound layer 37 include an injection (injecting) process, a spin coating process, a dispensing (dispensing) process, a film lamination (film lamination) process, an application process (application process), or a combination thereof. In some embodiments, a thermal curing process is used during the formation of the molding material layer 37.

Referring again to step S216, during the thinning of the molding compound material layer 37, the mask 35 may be removed (fig. 8B) or not (fig. 8C) by controlling the thinning process. Without removing the shield 35, the shield 35 on each electrode 26 and each conductive bump 28 can be directly used as a metal pad for electrically connecting the package structure 300 with an external circuit.

It is noted that the shield 35 disclosed herein provides at least two functions. The first function is to selectively etch the conductive layer 31 and the underlying conductive substrate 10 using the mask 35 as an etch-resistant material layer, as described in step S214. In another function, after the formation of the upper encapsulant layer 36 in step S216, the exposed shield 35 can be directly used as the metal pad 40 for electrically connecting the package structure 300 with an external circuit. In addition, in step S208, it is conventional to use a first mask for patterning the photoresist layer, and the photoresist layer is used as an etching-resistant material layer for selectively etching the conductive layer 31 and the underlying conductive substrate 10. However, this approach would require a second mask for forming the metal pad 40. Therefore, the manufacturing method disclosed by the invention can simplify the manufacturing process of the die package structure and reduce the production cost.

In operation S218, referring to fig. 9, after the upper encapsulant layer 36 is formed, if the mask 35 is removed, a plurality of metal pads 40 are formed on the exposed conductive bumps 28 and electrodes 26. In some embodiments, the metal pad is formed by an electroplating (electroplating) process, an electroless plating (electroless plating) process, a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, a printing (printing) process, or other applicable processes. In some embodiments, the metal pads are made of a solderable tin material. In some embodiments, the metal pad includes a nickel layer and a gold layer on the nickel layer.

Referring to fig. 10, after metal pads 40 are formed, bottom plate 10' is thinned to form a thinned bottom layer 10 ". The thinning process may include a Mechanical polishing (Grinding) process, a Chemical Mechanical Polishing (CMP) process, or other applicable processes.

In step S220, referring to fig. 11, the thinned bottom layer 10 ″ is patterned to form the circuit layer 50. For example, a photolithography process is used to form the patterned circuit layer 50. In some embodiments, the line width of the lines in the line layer 50 is about 50% to about 100% of the length or width of the die.

Continuing to step S222, referring to fig. 12, after the circuit layer 50 is formed, the lower encapsulant layer 38 is formed to cover the circuit layer 50, so that the lower encapsulant layer 38 substantially covers the circuit layer 50 to provide a protection function. In some embodiments, the lower encapsulant layer 38 is made of epoxy-based resin (EPOXY-BASED RESIN). In some embodiments, the formation of the lower encapsulant layer 38 includes an injection (injecting) process, a spin coating process, a dispensing (dispensing) process, a film lamination (film lamination) process, a coating process (application process), or other applicable processes. In some embodiments, a thermal curing process is used in the formation of the lower sealing layer 38.

Referring to fig. 12, after forming the lower encapsulant layer 38, an optional thinning process may be performed on the lower encapsulant layer 38, so that the thickness of the entire package structure may be controlled within a predetermined range. The thinning process may include a Mechanical polishing (grinding) process, a Chemical Mechanical Polishing (CMP), one or more other applicable processes, or a combination of the foregoing.

In step S224, a singulation process is performed to cut the upper encapsulant layer 36 and the lower encapsulant layer 38 along the cutting path S (i.e., the edge corresponding to the region a) shown in fig. 13, so as to obtain a plurality of package structures 300 separated from each other, as shown in fig. 14. In some embodiments, the package structure has a thickness H5 in a range from about 130um to about 200um, which can be adjusted according to product requirements, and the range of the thickness H5 is not limited thereto.

In various examples, the die package can be used to package a light sensing element or a light emitting element. However, the present invention is not limited to this application, and may be applied to various electronic components (electronic components) including integrated circuits such as active or passive elements, digital circuits, or analog circuits, for example, opto-electronic devices (optoelectronic devices), Micro-Electro-Mechanical systems (MEMS), Micro-fluidic systems (Micro fluidic systems), or Physical sensors (Physical sensors) that measure changes in Physical quantities such as heat, light, and pressure. In particular, semiconductor dies such as image sensors, light-emitting diodes (LEDs), solar cells (solar cells), radio frequency devices (RF circuits), accelerometers (accelerometers), gyroscopes (gyroscopes), micro actuators (micro actuators), surface acoustic wave devices (surface acoustic wave devices), pressure sensors (process sensors), or inkjet heads (ink printer heads) may be optionally packaged using a Wafer Scale Package (WSP) process.

In summary, the manufacturing method of the chip package structure of the present invention omits a Wire bond (Wire bond) process in the conventional manufacturing method, and has less selection limitation on the etching process, thereby simplifying the manufacturing process of the die package structure. Furthermore, the invention comprises a manufacturing method of the embedded type crystal grain packaging structure, which can achieve the miniaturization of the crystal grain packaging structure in the vertical direction and improve the heat dissipation effect of the power chip.

The foregoing has outlined features of many embodiments or examples so that those skilled in the art may better understand the present invention in various aspects. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention. Various changes, substitutions, and alterations can be made hereto without departing from the spirit and scope of the invention.

Claims

1. A method for fabricating a die package, comprising:

providing a conductive substrate with a plurality of grooves;

crystal grains are arranged in each groove;

forming a conductive layer covering the plurality of crystal grains and the conductive substrate;

forming a patterned light resistance layer on the conducting layer, wherein the patterned light resistance layer is provided with a plurality of openings to expose a plurality of areas of the conducting layer;

forming a shield on each of the regions of the conductive layer;

removing the patterned photoresist layer after forming the plurality of masks;

selectively etching the conductive layer and the conductive substrate thereunder to a predetermined depth using the plurality of masks to form a plurality of conductive bumps and a plurality of electrodes, wherein the remaining conductive substrate comprises a bottom plate, the plurality of electrodes are located on the bottom plate, and the plurality of conductive bumps are located on the plurality of dies; and

forming an upper sealing adhesive layer to cover the bottom plate and the plurality of crystal grains, wherein the plurality of shields, the plurality of conductive bumps or the plurality of electrodes are exposed out of the upper sealing adhesive layer.

2. The method of manufacturing a die package structure of claim 1, wherein the conductive substrate is made of copper.

3. The method of claim 1, wherein the conductive substrate has a first thickness and each of the recesses has a depth in a range of 45% to 55% of the first thickness.

4. The method of claim 1, wherein each of the shields comprises a nickel layer and a gold layer on the nickel layer.

5. The method of manufacturing a die package structure according to claim 1, further comprising:

after the upper sealing glue layer is formed, thinning the bottom plate to form a thinned bottom layer; and

and patterning the thinned bottom layer to form a circuit layer.

6. The method for manufacturing a die package structure according to claim 5, further comprising:

after the circuit layer is formed, forming a lower sealing glue layer to cover the circuit layer; and

and cutting the upper sealing adhesive layer and the lower sealing adhesive layer to obtain a plurality of packaging structures separated from each other.

7. The method of claim 6, wherein each of the package structures has a thickness in a range of 130um to 200 um.

8. The method of manufacturing a die package structure of claim 1, wherein forming the conductive layer comprises:

forming a copper seed layer using electroless plating; and

a copper plating layer is formed on the copper seed layer using electroplating.

9. The method of manufacturing a die package structure of claim 1, wherein forming the upper encapsulant layer covering the bottom plate and the plurality of dies comprises:

forming a sealant material layer covering the bottom plate, the plurality of crystal grains, the plurality of shields, the plurality of electrodes and the plurality of conductive bumps; and

and thinning the sealing material layer to expose the shields to the thinned sealing material layer.

10. The method of manufacturing a die package structure of claim 1, wherein forming the upper encapsulant layer covering the bottom plate and the plurality of dies comprises:

forming a sealant material layer covering the bottom plate, the plurality of crystal grains, the plurality of shields, the plurality of electrodes and the plurality of conductive bumps;

thinning the encapsulant layer, wherein the plurality of masks are removed such that the plurality of conductive bumps and the plurality of electrodes are exposed to the thinned encapsulant layer; and

and forming metal pads on the exposed conductive bumps and the electrodes.