SG11201401015PA - Pseudo-inverter circuit with multiple independent gate transistors - Google Patents

Pseudo-inverter circuit with multiple independent gate transistors

Info

Publication number
SG11201401015PA
SG11201401015PA SG11201401015PA SG11201401015PA SG11201401015PA SG 11201401015P A SG11201401015P A SG 11201401015PA SG 11201401015P A SG11201401015P A SG 11201401015PA SG 11201401015P A SG11201401015P A SG 11201401015PA SG 11201401015P A SG11201401015P A SG 11201401015PA
Authority
SG
Singapore
Prior art keywords
pseudo
inverter circuit
gate transistors
multiple independent
independent gate
Prior art date
Application number
SG11201401015PA
Other languages
English (en)
Inventor
Carlos Mazure
Richard Ferrant
Bich-Yen Nguyen
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11201401015PA publication Critical patent/SG11201401015PA/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
SG11201401015PA 2011-09-30 2011-09-30 Pseudo-inverter circuit with multiple independent gate transistors SG11201401015PA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2011/002823 WO2013045970A1 (en) 2011-09-30 2011-09-30 Pseudo-inverter circuit with multiple independent gate transistors

Publications (1)

Publication Number Publication Date
SG11201401015PA true SG11201401015PA (en) 2014-04-28

Family

ID=45349526

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201401015PA SG11201401015PA (en) 2011-09-30 2011-09-30 Pseudo-inverter circuit with multiple independent gate transistors

Country Status (6)

Country Link
US (1) US9496877B2 (zh)
KR (1) KR101880221B1 (zh)
CN (1) CN103843066B (zh)
DE (1) DE112011105691T5 (zh)
SG (1) SG11201401015PA (zh)
WO (1) WO2013045970A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2987710B1 (fr) 2012-03-05 2017-04-28 Soitec Silicon On Insulator Architecture de table de correspondance
US9762245B1 (en) * 2016-06-14 2017-09-12 Globalfoundries Inc. Semiconductor structure with back-gate switching
KR102467312B1 (ko) * 2018-10-15 2022-11-14 삼성전자주식회사 고전압 스위치 회로 및 이를 포함하는 비휘발성 메모리 장치
CN117095714A (zh) * 2022-05-13 2023-11-21 长鑫存储技术有限公司 驱动电路及其驱动方法、存储器
CN116863873B (zh) * 2023-09-05 2023-11-21 惠科股份有限公司 显示驱动电路、显示驱动方法及显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030151077A1 (en) 2002-02-13 2003-08-14 Leo Mathew Method of forming a vertical double gate semiconductor device and structure thereof
US7274618B2 (en) 2005-06-24 2007-09-25 Monolithic System Technology, Inc. Word line driver for DRAM embedded in a logic process
US7382162B2 (en) * 2005-07-14 2008-06-03 International Business Machines Corporation High-density logic techniques with reduced-stack multi-gate field effect transistors
US7592841B2 (en) 2006-05-11 2009-09-22 Dsm Solutions, Inc. Circuit configurations having four terminal JFET devices
US7697365B2 (en) * 2007-07-13 2010-04-13 Silicon Storage Technology, Inc. Sub volt flash memory system
US7940572B2 (en) * 2008-01-07 2011-05-10 Mosaid Technologies Incorporated NAND flash memory having multiple cell substrates
US7969226B2 (en) * 2009-05-07 2011-06-28 Semisouth Laboratories, Inc. High temperature gate drivers for wide bandgap semiconductor power JFETs and integrated circuits including the same
KR20110029402A (ko) * 2009-09-15 2011-03-23 삼성전자주식회사 비휘발성 메모리 장치, 및 그것을 포함한 메모리 시스템, 그것의 쓰기 전류 제어 방법
US8270222B2 (en) * 2009-09-24 2012-09-18 Macronix International Co., Ltd. Local word line driver of a memory
FR2958441B1 (fr) * 2010-04-02 2012-07-13 Soitec Silicon On Insulator Circuit pseudo-inverseur sur seoi

Also Published As

Publication number Publication date
US20140225648A1 (en) 2014-08-14
CN103843066A (zh) 2014-06-04
KR101880221B1 (ko) 2018-07-20
DE112011105691T5 (de) 2014-12-04
KR20140079408A (ko) 2014-06-26
US9496877B2 (en) 2016-11-15
CN103843066B (zh) 2016-08-17
WO2013045970A1 (en) 2013-04-04

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