SG10201408593TA - Processing system and method for large scale substrates - Google Patents
Processing system and method for large scale substratesInfo
- Publication number
- SG10201408593TA SG10201408593TA SG10201408593TA SG10201408593TA SG10201408593TA SG 10201408593T A SG10201408593T A SG 10201408593TA SG 10201408593T A SG10201408593T A SG 10201408593TA SG 10201408593T A SG10201408593T A SG 10201408593TA SG 10201408593T A SG10201408593T A SG 10201408593TA
- Authority
- SG
- Singapore
- Prior art keywords
- processing system
- large scale
- scale substrates
- substrates
- processing
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SG10201408593TA SG10201408593TA (en) | 2014-12-22 | 2014-12-22 | Processing system and method for large scale substrates |
PCT/SG2015/050243 WO2016105277A1 (en) | 2014-12-22 | 2015-07-30 | Processing system and method for large scale substrates |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SG10201408593TA SG10201408593TA (en) | 2014-12-22 | 2014-12-22 | Processing system and method for large scale substrates |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201408593TA true SG10201408593TA (en) | 2016-07-28 |
Family
ID=56151135
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201408593TA SG10201408593TA (en) | 2014-12-22 | 2014-12-22 | Processing system and method for large scale substrates |
Country Status (2)
Country | Link |
---|---|
SG (1) | SG10201408593TA (en) |
WO (1) | WO2016105277A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI820522B (en) * | 2020-12-15 | 2023-11-01 | 新加坡商洛克系统私人有限公司 | Method and system for ic unit singulation and sorting |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04321242A (en) * | 1991-04-22 | 1992-11-11 | Mitsubishi Electric Corp | Chip stocker |
JPH1022365A (en) * | 1996-07-04 | 1998-01-23 | Mitsubishi Electric Corp | Positioning apparatus |
-
2014
- 2014-12-22 SG SG10201408593TA patent/SG10201408593TA/en unknown
-
2015
- 2015-07-30 WO PCT/SG2015/050243 patent/WO2016105277A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2016105277A1 (en) | 2016-06-30 |
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