SE9903338D0 - Semiconductor structure and fabrication method - Google Patents

Semiconductor structure and fabrication method

Info

Publication number
SE9903338D0
SE9903338D0 SE9903338A SE9903338A SE9903338D0 SE 9903338 D0 SE9903338 D0 SE 9903338D0 SE 9903338 A SE9903338 A SE 9903338A SE 9903338 A SE9903338 A SE 9903338A SE 9903338 D0 SE9903338 D0 SE 9903338D0
Authority
SE
Sweden
Prior art keywords
dielectric layer
trench
edge
forming
shallow
Prior art date
Application number
SE9903338A
Other languages
Swedish (sv)
Other versions
SE518533C2 (en
SE9903338L (en
Inventor
Hans Norstroem
Carl Bjoermander
Ted Johansson
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE9903338A priority Critical patent/SE518533C2/en
Publication of SE9903338D0 publication Critical patent/SE9903338D0/en
Priority to TW088117804A priority patent/TW459336B/en
Priority to JP2001524144A priority patent/JP5172060B2/en
Priority to CA002385031A priority patent/CA2385031A1/en
Priority to KR1020027003288A priority patent/KR20020030816A/en
Priority to PCT/SE2000/001690 priority patent/WO2001020664A1/en
Priority to AU75654/00A priority patent/AU7565400A/en
Priority to EP00964830.4A priority patent/EP1212792B1/en
Priority to CNB008158916A priority patent/CN1252809C/en
Priority to US09/662,842 priority patent/US6413835B1/en
Publication of SE9903338L publication Critical patent/SE9903338L/en
Priority to US10/119,047 priority patent/US6690080B2/en
Publication of SE518533C2 publication Critical patent/SE518533C2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)

Abstract

Shallow and deep trenches are formed by forming (a) shallow trenches on a substrate, (b) dielectric layer, (c) opening(s) (33) in the dielectric layer using a mask (22) with an edge aligned to an edge (26) of the shallow trench, (d) a spacer (32) in and along the edge of the shallow trench, and (e) a deep trench (34) in the opening using the dielectric layer as a hard mask. Formation of shallow and deep trenches for isolation of semiconductor devices in the integrated circuit comprises: forming shallow trench(es) using a first mask formed on a substrate; forming a dielectric layer (20) of a predetermined thickness; forming opening(s) in the dielectric layer using a second mask (22) with an edge of the second mask aligned to an edge of the shallow trench with a maximum misalignment of half the predetermined thickness of the dielectric layer; forming a spacer in the shallow trench and along the edge of the trench; and forming a deep trench in the opening using the dielectric layer as a hard mask. The width of the spacer is equal to the predetermined thickness of the dielectric layer. The deep trench extends further into the substrate and is self-aligned to the shallow trench. An Independent claim is also included for an integrated circuit for radio frequency applications fabricated using the above method.
SE9903338A 1999-09-17 1999-09-17 Formation of shallow and deep trenches for isolation of semiconductor devices involves forming shallow trench(es), dielectric layer, opening(s) in dielectric layer, spacer, and deep trench in opening SE518533C2 (en)

Priority Applications (11)

Application Number Priority Date Filing Date Title
SE9903338A SE518533C2 (en) 1999-09-17 1999-09-17 Formation of shallow and deep trenches for isolation of semiconductor devices involves forming shallow trench(es), dielectric layer, opening(s) in dielectric layer, spacer, and deep trench in opening
TW088117804A TW459336B (en) 1999-09-17 1999-10-14 Semiconductor structure and fabrication method
CNB008158916A CN1252809C (en) 1999-09-17 2000-09-04 Self-aligned method for forming deep trenches in shallow trenches for isolation of semiconductor devices
KR1020027003288A KR20020030816A (en) 1999-09-17 2000-09-04 A self-aligned method for forming deep trenches in shallow trenches for isolation of semiconductor devices
CA002385031A CA2385031A1 (en) 1999-09-17 2000-09-04 A self-aligned method for forming deep trenches in shallow trenches for isolation of semiconductor devices
JP2001524144A JP5172060B2 (en) 1999-09-17 2000-09-04 Self-aligned method for forming deep trenches in shallow trenches for semiconductor device isolation
PCT/SE2000/001690 WO2001020664A1 (en) 1999-09-17 2000-09-04 A self-aligned method for forming deep trenches in shallow trenches for isolation of semiconductor devices
AU75654/00A AU7565400A (en) 1999-09-17 2000-09-04 A self-aligned method for forming deep trenches in shallow trenches for isolation of semiconductor devices
EP00964830.4A EP1212792B1 (en) 1999-09-17 2000-09-04 A self-aligned method for forming deep trenches in shallow trenches for isolation of semiconductor devices
US09/662,842 US6413835B1 (en) 1999-09-17 2000-09-15 Semiconductor structure and fabrication method of shallow and deep trenches
US10/119,047 US6690080B2 (en) 1999-09-17 2002-04-10 Semiconductor structure for isolation of semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9903338A SE518533C2 (en) 1999-09-17 1999-09-17 Formation of shallow and deep trenches for isolation of semiconductor devices involves forming shallow trench(es), dielectric layer, opening(s) in dielectric layer, spacer, and deep trench in opening

Publications (3)

Publication Number Publication Date
SE9903338D0 true SE9903338D0 (en) 1999-09-17
SE9903338L SE9903338L (en) 2001-03-18
SE518533C2 SE518533C2 (en) 2002-10-22

Family

ID=20417037

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9903338A SE518533C2 (en) 1999-09-17 1999-09-17 Formation of shallow and deep trenches for isolation of semiconductor devices involves forming shallow trench(es), dielectric layer, opening(s) in dielectric layer, spacer, and deep trench in opening

Country Status (2)

Country Link
SE (1) SE518533C2 (en)
TW (1) TW459336B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104934530B (en) * 2014-03-19 2018-09-21 中芯国际集成电路制造(上海)有限公司 A kind of manufacturing method of semiconductor devices

Also Published As

Publication number Publication date
SE518533C2 (en) 2002-10-22
SE9903338L (en) 2001-03-18
TW459336B (en) 2001-10-11

Similar Documents

Publication Publication Date Title
TW343380B (en) Threshold voltage tailoring of corner of MOSFET device
KR100941742B1 (en) A method of forming differential spacers for individual optimization of n-channel and p-channel transistors
US6551937B2 (en) Process for device using partial SOI
SE9904310D0 (en) Method in the production of a silicon bipolar transistor
US5895243A (en) Semiconductor processing method of providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors and integrated circuitry having adjacent electrically isolated field effect transistors
US6787874B2 (en) Semiconductor device
CN103377940B (en) A kind of P-type transmission gridistor for SRAM and preparation method thereof
SE9903338D0 (en) Semiconductor structure and fabrication method
US5963798A (en) Fabrication method of CMOS device having buried implanted layers for lateral isolation (BILLI)
KR20000003951A (en) Isolation method of soi devices
EP1187193A3 (en) Semiconductor integrated circuit device and method of manufacturing the same
WO2005022608A3 (en) Siliciding spacer in integrated circuit technology
WO2002017399A8 (en) Semiconductor arrangement and method for production thereof
KR20030008666A (en) MOS transistor and forming method thereof
GB2377818A (en) Flash memory array and a method and system of fabrication thereof
SE0002389D0 (en) Transistor device and fabrication method thereof
KR970072295A (en) Method for forming a separation film of a semiconductor element
TW429512B (en) Semiconductor device and method for manufacturing the same
KR20060077641A (en) Method for fabricating rf mos semiconductor device
KR960005886A (en) Bipolar Device Manufacturing Method
Inokawa et al. A submicrometer lifted diffused-layer MOSFET
CA1057415A (en) Self-aligned cmos process for bulk silicon and insulating substrate device
KR20010004030A (en) method of manufacturing semiconductor device
KR950021396A (en) Field oxide film manufacturing method
KR20020044862A (en) Method For Forming The MOS-Transistor