TW459336B - Semiconductor structure and fabrication method - Google Patents

Abstract

In the fabrication of an integrated circuit, particularly an integrated circuit for radio frequency applications, a method for forming shallow and deep trenches for isolation of semiconductor devices comprised in said circuit, comprising providing a semiconductor substrate (10); optionally forming a first dielectric layer (14) on said substrate; forming at least one shallow trench (18) by using a first mask (16), said shallow trench extending into said substrate; forming a second dielectric layer (20) of a predetermined thickness (2x) on the structure obtained subsequent to the step of forming at least one shallow trench; forming at least one opening (33) in said second dielectric layer by using a second mask (22) with an edge (30) of said second mask aligned to an edge (26) of said shallow trench with a maximum misalignment (+/- x) of half the predetermined thickness (2x), said opening extending within the shallow trench to the bottom (18a) thereof, whereby a spacer (32) of a width equal to the predetermined thickness (2x) is formed in said shallow trench and along said edge thereof; and forming a deep trench (34) in said opening by using said second dielectric layer as a hard mask, said deep trench extending further into said substrate and being self-aligned to said shallow trench.

Description

459336 Qiu, Mingming Mingming (i) The calling technology, but the domain of wood invention is generally related to the body circuit 丨 semiconductor devices through the use of isolation junction isolation, thus leading to increased packaging density and isolation. In particular, the present invention relates to a method for manufacturing a semiconductor structure, including a shallow trench isolation region and a deep trench isolation region, in the semiconductor structure itself, and to a integrated circuit including the semiconductor structure. Description of related technologies All integrated electronics involve connecting isolated devices via specific motor connection paths. This device isolation scheme is therefore one of the important components when manufacturing integrated circuits. Many different schemes have been developed over the years. Parameters such as minimum isolation space, surface planarity, defect density, program complexity, and electrical characteristics, such as DC and high frequency characteristics, affect special application and program technology program choices. Platform isolation, interface isolation, and locos (silicon local oxidation) isolation are common techniques. Please refer to Chapter 2 of the “VLS I Silicon Processing” published by Wolff in 1990 for program integration. For example, the characteristics of ξ generation have reduced the number of high-integrity integrated circuits (ULS I) and ultra-large integrated circuits. It is necessary to reduce disadvantages such as package density, leakage current between devices, and latch-up, which are related to earlier isolation techniques. Shallow and deep sentence isolation has become very popular. Although depending on the etching and filling process steps, they provide a considerable reduction in area improvement when circuit components need to be isolated, and storage capabilities such as DRA M memory and technology * The formation of these trenches is to remove silicon and fill it by dry etching Appropriate dielectric or conductive material. Shallow trench isolation (ST I), which is used to replace LOCOS isolation, usually has a depth of tens of microns and is used for isolation between device components. shallow

厶 5 9 3 3 6 JL 'f / i-mv / jf] (2) 沭 Isolation is a piece of-near description' such as " Choices and challenges of shallow flood isolation 1 1989 Ί / 丨 Semi-floating body solid boundary P. 6-9. Deep trenches usually have a depth slightly larger than micrometers, and are mainly used to isolate different devices and device groups (ditch wells) in CMOS / B i CMOS technology to form vertical cells and form high-conductivity contacts. Please guess that McGill Hill published in New York in 1999, G, by Zhang and Zhu Suoqiao " 111 ^ 1 Technology "page 355-3 5 7 and \\『 0 9 7/3 5 3 4 4 (Inventors: Jassin and Norstron). The trenches are filled with oxide, polycrystalline silicon or other materials, and the surface is flattened, either by dry etching or by chemical mechanical polishing (CMP). Squeez and Zhou Bell's U.S. Pat. No. 4,99,4,06,6 describes a method for forming a shallow trench and self-aligning a deep isolation trench on an integrated circuit. Although the deep trench can be self-aligned Just to the edge of the device area, these structures use a polycrystalline silicon nitride stack to form device isolation using LOCOS, with—

Large side erosion, high temperature boundaries, and the results of a non-planar surface D ° US Patent 5,6 9 1, 2 3 2 discloses a method for forming shallow and deep trench isolation by combining the two. First, a shallow trench is formed using a first layer, and then a deep trench is formed using a second photomask. The entire structure is extremely filled with oxide and flattened. The product / Mugou mask must be aligned with the shallow trench mask, so that less package current can be obtained when the structure is formed. Furthermore, filling narrow and deep trenches usually requires silicon and back etching, which is not in this description. The method described in U.S. Patent No. 5,8,9,2,53 is used to form a shallow trench and to fill the isolator. The deep groove is self-kappa / inner beta which is formed only in a single photomask step. The groove is formed

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L · '^ «/ 1 Wa / 1 (after 3J, a general method of ifl charging is used. Although these patents teach how to set up a deep trench line yf -f-in a shallow trench, the method uses only a single Photomask, and it is impossible to use shallow grooves without any deep grooves. The width of the deep grooves is set by the width of the shallow groove openings and the width of the separator. If the shallow groove openings are different, the deep grooves will be etched and filled. Difficult or even impossible. Summary of the Invention Results An object of the present invention is to provide a method for manufacturing an integrated circuit, in particular, the integrated circuit is used to shield the electrical frequency of the line and is used to form a shallow trench and a deep trench to isolate the circuit The semiconductor device contained therein overcomes at least part of the problems of the prior art. Another object of the present invention is to provide a manufacturing method and allow a deep trench to be placed in a shallow trench area, with an adjustable distance from the edge of the shallow trench to the deep trench, At the same time, shallow trench regions are allowed to form without the need for deep trenches. Another object of the present invention is to provide the method with enhanced scale scalability characteristics leading to an increased packaging density. Another object of the present invention is to provide the method with The increased elasticity of the product and its compatibility with several technologies. These objects, according to one aspect of the invention, are accomplished by a method comprising the following steps: • providing a semiconductor matrix; • selectively forming A first dielectric layer on the substrate; forming at least one shallow trench on the first dielectric layer or on the substrate, which is formed on the first dielectric layer using a first photomask, the Shallow grooves extend into the matrix;

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V. Booming Mingming (4 J * forming a second dielectric layer with a thickness of 2 mm, 2 X, caused by the step of forming a shallow trench in the structure; • .¾ by using a second light leather Formed on the second dielectric layer to 'form at least one hole in the second dielectric t layer, and an edge having the second photomask is aligned to the shallow with a maximum misalignment of one half of ten / -X An edge of the groove, the opening extends the shallow groove to the bottom of the substrate, and an isolator having a width equal to a predetermined thickness of 12x is formed in the shallow groove and along the edge; and The two dielectric layers form a deep trench in a hard mask and the deep trench extends into the substrate and is aligned to the shallow trench by itself. In addition, an object of the present invention is to provide a method for manufacturing Semiconductor structure According to a second aspect of the present invention, a semiconductor structure is provided that includes a semiconductor substrate: at least one shallow trench extends vertically into the substrate; a deep trench is laterally located in the shallow trench, and the deep trench extends vertically into the substrate. Where the deep trench is self-aligned into the shallow trench a controlled lateral distance from the An edge of the trench and an edge of the deep trench, and a horizontal phase extension of the shallow and deep trenches are individually selected. An advantage of the present invention is that the distance between the deep and shallow trenches is fixed and is determined by the thickness of the deposited dielectric layer It is easy to control. Another advantage of the present invention is that the distance between the deep and shallow trenches is minimized to obtain an increased packaging density of the integrated circuit, while providing a step in between to prevent deep trench processing and operating area interference. Other advantages and features of the present invention will be disclosed in the detailed description of the following specific examples:

459336 V. Description of the invention (5) Brief description of the m-diaphragm The invention will be more clearly understood through the detailed description of the invention with a small example and Figures 1-11 for illustrative purposes only, and is not a limitation of the invention. Nos. 3 and 5-8 are enlarged cross-sectional views of a semiconductor structure during the processing of the present invention. FIG. 4 is a view of a port of a semiconductor structure during processing by the present invention. 9-9 is an image of a cross-section of a port of a semiconductor structure during processing by the present invention. Detailed description of specific examples In the following description, for the purpose of illustration and not limitation, specific details are stated, such as special hardware, applications, technologies, etc., to provide a complete understanding of the present invention. In any case, it is obvious that the present invention can be practically applied to other specific examples not related to the specific details. In other examples, detailed descriptions of known methods, protocols, equipment, and circuits are omitted so as not to obscure detailed descriptions of the present invention. Senge Tub 11, a specific example of the invention of a processing sequence, which includes the formation of deep and shallow trenches, filling trenches, and planarization, is described in detail. Areas may have been formed in the starting material before forming isolation, secondary control II, recesses, or other equipment. Anyway, in this step where the process of the invention is started, the surface of the silicon wafer is cleaned and the top layer of silicon is removed. See Figure 1. A shallow trench-shaped hard mask formation is revealed:. The shallow trench mask is formed through the silicon oxide surface 10 to form a layer 12 of thermal silicon dioxide with a typical thickness of 100 angstroms. Secondly, a silicon nitride layer with a thickness of about 2000 angstroms

Page 丨 0 4 5 9 33 6 V. Inventing Yueming (6) --- Y is deposited by chemical vapor deposition (CVD). Other thickness bonding and / or light materials are possible.夂 -ren called see Figure 2 ′ The formation of a shallow trench is considered. A photoresist 16 is exposed on the second reaction layer 14 and exposed using a first photomask, the so-called trench light, which is etched by four shallow trenches. In this case, it is preferably anisotropic anisotropy, which is performed via reactive ion etching ({UE), and then nitride / oxidized into layers 12 and 14 and enters the silicon substrate 10 to form a vertical shallow trench 8. The groove 18 has a fortunate depth of 0.2-0.7 // 111, or more typically 0.3-0.6 to 111, which is 10 a from the surface of Shixi. The photoresist 16 is removed to etch the shallow trench 6. Referring next to Figures 3 and 4, a hard mask is described. ~ 2x thick silicon oxide is deposited, preferably conforming, such as via CVD, at the top of the structure, such as the reserved port of the nitride layer 14 and the shallow trench] 8 within 5 which is preferably the oxide layer 2 0 is Deposition is consistent with other reticle and areas where etching will be reduced. The photoresist 22 is used, and a so-called grooved photomask using a second photomask is used, which is connected with the port of the oxide layer 20 to define the one or two openings 24 and a width w. The arrangement of the first and second photomasks is shown in Fig. 4, respectively, which shows the above-mentioned semiconductor structure. The lateral definitions of the edges and openings of the shallow trenches will form the deep trenches as described in 26 and 28 respectively. '' The openings of the trench mask can be placed anywhere in the shallow trench area. The width of the deep trench can be selected by using different mask sizes. It is usually preferred to use a trench (thickness) 'with a fixed lateral area, preferably 1 to m or less; such as the occurrence of non-uniform silver engraving and the difficulty of filling and planarizing the deep trench. A feature of the present invention is the alignment of the mask edge 30 to the shallow groove edge 26, which

O: \ 60 \ 60S47.PTD Page II 459336 Five, howling 1¾ Ming (7) so that 彳 ί can be placed by the depth of the oxide 2 x set the depth of the deep trench, one of the more typical examples is 1 Between 0 0 0 and 4 0 0 0 0, and typically 2 500 0 Angstroms. By the way, the height 1 of the shallow trench 18, the gaseous layer 丨 2 and the nitride layer 1 4 (such as the overall etching depth when the shallow trench 18 is formed) and the thickness UX of the silicon oxide layer 20 satisfy the following relationship:

II y 2 X in circles 3 and 4 as detailed for mask alignment and oxide thickness. Assuming that the oxide is 100% consistent (thickness in each step) with a thickness of 2 X, the trench mask 30 is positioned with a heavy # X, and the trench mask 3 0 is weighted with a weight from the silicon nitride edge 2 6 Swallow X positioning, its positioning is determined by the trench mask. A modern stepper can align the mask more accurately: or better than 1 (] 0 0 angstroms. Secondly referring to Figure 5, the formation of the oxide isolator 32 is considered. The oxide 20 is passed through the reactive ion Etching (RIE) etch to define trench openings 3 3a extending to the surface of the bottom of the shallow trench. Similarly, an inverted isolator is formed at the shallow trench edge of the layer 20 port, which has a 2x thickness. By controlling the oxygen {I: layer thickness 2 X, the distance from the shallow trench edge to the deep trench opening can be adjusted. On the top of the nitride layer 14, the oxide layer 20 is protected by a photoresist mask And this oxide will later serve as a hard mask for these areas in the following etching steps. The oxide layer 20 is also confined to the port in the shallow trench area, where no deep trench is formed = the light is being etched After the resist has been removed, please refer to FIG. 6. A deep trench 34 is formed by etching, using the oxide 20 and the spacer 32 as a hard mask. The width of the oxide barrier 3 2 is defined from The distance from the deep groove 34 to the actuating area. The depth of the deep groove is at least several microns, and preferably at least 5 microns.

Page 12 459336 V. # 明 说明 (8) Now the ginseng room __ Figure 7 ’The hardened leather 2 0, 3 2 is used to form the deep groove 3 2 is removed, as in 丨 丨 卩. As a result, the crater filling and flattening the trench area can be completed by several methods known to the skilled artisan. This example is an example. The procedure is continued by performing a linear oxidation. And unwanted t-gas effects. This system is completed by growing a thin C 2 0 0-3 0 0 angstrom thermal oxide 3 6 at high temperature (> 1 0 0 ° C). Because the isolator has been removed, a small "black mouth" will be formed in the oxide layer 12 under the nitride layer 14 and it will be added to the corner surround. Please refer to Figure 7 below. In Fig. 8, the trench is filled with 2 000 angstrom thickness layers of 3 8 and 15 0 angstrom polycrystalline silicon 40 in a conventional manner. The polycrystalline silicon is then etched to remove all polycrystalline silicon from the shallow trench region. Alternatively, a dielectric is used to fill the trenches instead of polycrystalline silicon. Finally, the remaining shallow trenches are filled with, for example, CVD oxide 42, and planarized by dry etching or chemical mechanical polishing. The final structure is shown in Figure 8 This procedure is carried out to form actuating devices, etc., which are not shown in the figure and will be explained in this description. Next, referring to FIG. 9-1 1, the horizontal direction of a port of a semiconductor structure during processing according to the present invention. The SEM (scanning electron microscope) image of the cross section will be briefly explained. The structure obtained before trench filling is shown in Figures 9 and 10. Please note that the oxide / nitride at the top is not visible. In Figure 9, the electron Scanning microscope showing shallow grooves without any deep grooves ( Left and rightmost structure) and the other shallow well region and the two self-aligned to a deep trench region (k edge at the center) is.

Page 13 4 59 33 6 i, description of the invention (9) The frame area # is shown by 44 of the structure corresponding to the circles 1-3 and 5. In Fig. 10, the micro-enclosed device area 46 is used for two bipolar transistors 4, 8, 50 as shown in the figure, and the deep groove is close to the collector contact area 5 2 for self-alignment to The shallow clearing male edge ~ Finally, FIG. 1 丨 shows a sequence of a SEM image of the structure etched to the back of the multi-prints from the shallow; the sea area is removed. After the figure is carved, the structure is represented by 5 4 and a thickness of 2 0 0 angstrom T EOS layer on the top of the nitride / oxide layer and the area in the trench as shown in 56. In summary, the present invention uses an additional Photomask (ditch reticle) steps and making it compatible with shallow trench isolation to produce a flat surface. Deep trenches can be placed anywhere in the shallow trench area. In addition, by forming a chemical isolator in the shallow trench, the deep trench can form a self-alignment to the shallow trench. The distance from the deep trench to the actuation area can be controlled by the thickness of the hard mask oxide. This maximizes the package density and prevents the trench from reaching the operating area, which can cause leakage currents, reduce breakdown voltage, or other unwanted effects. The invention has the following advantages due to rolling 1. The overlap of ST I between the deep groove and the actuating area (such as the distance between the edge of the deep groove and the edge of the shallow groove, 2x) is minimized and can be easily controlled. The isolation of the deep groove from the actuating area determined by the edge of ST I is self-aligned to prevent the deep groove processing from disturbing the pressure generated by the actuating area. This isolation is determined by the thickness of the deep trench hard mask (and possibly combined with the STI stack height, such as * shallow trench depth). .. • The groove positioning is fixed and determined by the additional reticle (groove reticle). • The additional mask is positioned on the oxide isolator produced by the hard mask

Page 14 459336 V. Explanation of Mingming (丨 〇) Inner core is not overlapped (isolation width 2χ gives an allowable misalignment + /-X) 稃 稃 away from the gas separator is etched in the deep groove to allow the deep groove Synchronous corner rings and ST 丨 approach the action area (black mouth). It is clear that the invention can be varied in many ways. Such changes are not deemed to depart from the scope of the invention. All such improvements are well understood by those skilled in the art and may be included in the scope of such patent applications.

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Claims (1)

453336, _Case No. 88117804_year + Jinyue > Heart correction __ τ, patent application scope 1. A type of integrated circuit used to form shallow and deep trenches for isolation when manufacturing one of integrated circuits, especially for radio frequency applications The method for a semiconductor circuit included in the circuit is characterized by the following steps: providing a semiconductor substrate (1 0); forming at least one shallow trench (1 8) by using a first photomask (16) formed on the substrate; The shallow trench extends into the substrate; a dielectric layer (20) of a predetermined thickness (2X) is formed on the obtained structure to form at least one shallow trench; and a second light is formed on the dielectric layer by using The cover (22) forms at least one opening (33) in the dielectric layer and an edge (30) of the second photomask with a maximum mismatch of a predetermined thickness (2x) of the dielectric layer (+/- X) Align i with an edge (2 6) of the shallow trench, the opening extends in the shallow trench to the bottom end (18a), and is separated by an isolator (32) having a width equal to a predetermined thickness (2x). Formed in the shallow trench and along the edge; and forming a deep trench by using the dielectric layer as a hard mask (34) The open hole, which extends deep into the matrix and the other is self-aligned to the shallow trench. 2. The method according to item 1 of the scope of patent application, characterized in that it passes through the step of selecting a predetermined thickness (2x) between the dielectric layer (20) and the edge (28) of the isolator, so the deep trench (3 4), And the edge (2 6) of the shallow trench (1 8) depends on the semiconductor device included in the circuit. 3. The method according to item 1 or 2 of the scope of patent application, characterized by the step of forming the dielectric layer (20) by uniform deposition, preferably chemical vapor deposition. 4. The method of claim 1 in the scope of patent application, characterized in that O: \ 60 \ 60847.ptc Page 1 2001.08.17.017 5 9 3 3 6 _Case No. 88117804_f Month ___ Sixth, the scope of patent application is a dielectric layer (1 4), especially a silicon nitride A step of forming a shallow trench (18) on the substrate. 5. The method according to item 1 of the scope of patent application, characterized by the step of forming an oxide layer (12), in particular a thermal oxidation layer, before the substrate forms at least one shallow trench (18). 6. The method according to item 1 of the scope of patent application, characterized by forming a deep oxide trench (3 4) on the structure obtained by forming an oxide linearity (3 6), especially a thermal oxide linearity. The corner surrounds the steps that are separate from the sharp corners of the shallow and deep grooves (18, 34) at the same time. 7. The method according to item 1 of the scope of patent application, characterized in that an isolation layer (38), preferably a TEOS layer is deposited, and the shallow and deep trenches (18, 34) are filled with semiconductors (4 0) or a step of isolating the material and removing the semiconductor material from the shallow trench (18). 8. The method according to item 7 of the patent application, which is characterized by depositing an isolation layer (42), preferably a CVD oxide, in the shallow trench (18) and planarizing the upper surface of the isolation layer. step. 9. The method of claim 1 in the scope of patent application, characterized in that the semiconductor substrate (10) is made of silicon. 10. The method according to item 1 of the scope of patent application, characterized in that the shallow trench (18) is subjected to etching, preferably non-anisotropic reactive ion etching. 1 1. The method according to item 10 of the scope of patent application, characterized in that after the step of forming at least one shallow trench, the shallow trench (18) is etched to a depth exceeding the thickness of the formed dielectric layer (2x ). 1 2. The method according to item 1 of the scope of patent application, characterized in that the shallow trench o: \ 60 \ 60847.ptc Page 2 2001.08.17.018 4 5 9 33 6 Amendment_ Case No. 88117804 Six 'application patent scope (18) is formed to a depth of 0.2-0.7 / zm from the surface of the silicon substrate (10a) . 1 3. The method according to item 1 of the scope of patent application, characterized in that the dielectric layer formed after the step of forming at least one shallow trench is an oxide layer, preferably a TEOS layer, to a preferably about 100 The predetermined thickness (2x) of 0-4 0 0 0 angstroms = 14. The method according to item 1 of the scope of patent application, characterized in that at least one opening (3 3) in the dielectric layer (2 0) is formed in at least one After the shallow trench formation step, it is formed by touch engraving, preferably reactive ion money engraving. 15. The method of claim 1, wherein the deep trench (3 4) is formed to at least a few microns by etching. 16. A semiconductor structure, an integrated circuit, especially a radio frequency application integrated circuit, to isolate the semiconductor circuit contained in the circuit, a feature is that it contains a semiconductor substrate (10); at least a shallow trench (18) Extending vertically into the substrate; a deep groove (3 4) is transversely inside the shallow groove, and the deep groove extends vertically into the substrate, wherein the deep groove is self-aligned into the shallow groove in the shallow groove (2 6) A lateral distance is controlled between an edge of and the edge (28) of the deep trench, and the lateral extensions of the shallow and deep trenches are independently selected. 1 'An integrated circuit, especially a radio frequency application integrated circuit, which is characterized in that it contains a semiconductor structure such as one of the 16th in the scope of patent application. O: \ 60 \ 60847.ptc Page 3 2001.08.17.019