CA1057415A - Self-aligned cmos process for bulk silicon and insulating substrate device - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

The method for fabrication of a self-aligned gate CMOS structure which employs no additional masking steps as compared to the standard CMOS fabrication process, this improved process providing the advantages of self-alignment between the N+ and P+ source and drain diffusions with respect to their gate regions, and metal contact openings which do not overlap the edges of the P+ or N+ source and drain regions. The self-aligning gate region is defined by a silicon nitride gate layer. Several embodiments of the novel process are described.

Description

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Tllis applica~ion i.s a dlvisional application of Canadian application serial No. 246,453, filed February 24, 1976.
~ACKGROUND OF TIIE PRESENT INVENTION
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In a collventional complementary metal oxide semi-conductor (CMOS) integrated circuit fabrication, and assuming an N type semiconductor substrate, the first stage includes the photoresist masking and etching of the silicon oxide layer on the substrate to form openings therein for the P- diffusion in~o the N substrate. The second masking and etching of the silicon oxide layer is to form openings for the P+ diffusion regions forming the drain and source for the P channel gate devices. The third masking and etching step in the silicon oxide layer is utilized to form the openings for the source and drain N+ diffusions for the N channel gate devices in the P- diffused regions. A fourth masking and etching step is used to form the openings through the silicon oxide at the gate regions of the P channel and the N channel devices, the thin gate oxide film thereafter being thermally grown. The -: .
fifth masking and etching step is provided to form the contact openings through the silicon oxide layer to the various P+
and N+ source~ drain and substrate regions. The sixth masking step is used to form the metal interconnections between the various contact openings and to define the metal gate electrodes over the thin gate oxide film in the channel regions of the gate devices. In this conventional CMOS fabrication, the - -gate regions for the various gate devices are defined after -the P+ and N+ diffusion , i.e., Wit}l the fourth masking step. It is necessary to make oversized gate openings to be sure that the gate regions overlap the P+ source and drain regions and the N+ source and drain regions, taking into consideration the normal amount of mask misalignment

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3 into consideration this normal tolcrance, and tl1us an overlap

4 o tlle gate region with the source and drain regions is produced.

5 This overlapping of the gate and the drain and source rcgions ;~

6 introduces a large parasitic capacitance between the metzl gate

7 elcctrode and the P+ and N~ regions separated by the thin gate

8 oxide layer. This parasitic capacitance reduces the speed of

9 the integrated circuit in operation. It is therefore desirable ;~
that a fabrication technique be employed which produces no 11 overlap between the gate and the source and drain regions so 12 that the metal gate electrode over the source and drain regions 13 is separated therefrom by a thick oxide insulation layer rather 14 than the thin gate oxide layer, thus eliminating parasitic 15 capaci~ance. ;~
16 A second undesirable feature of the conventional CMOS
17 fa~rication results from the misalignment between the N~, P+ ;
l8 and contact opening mask and can severely limit ~he yield of 19 a large size CMOS circuit. This misalignment dictates that the contact openings must be deslgned well inside the P+ and 21 N+ diffusion areas in order to compensate the misalignment and 22 mask dimension variation. In ordcr to provide for this variation 23 in contact location, it is necessary that the area of ~he CMOS -24 s*ructure ~e greater tha11 desired~
A third undesirable feature of the conventional C~SOS process 26 is that the gate oxidation is performed ater the N~ and P~
27 diusion steps and, since this gate oxidation is perormed 28 at a relatively high temperature, the P~ and N+ junction depths .. . . .
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1 canllot be k~pt as shallow as desired and tilc resulting suracc 21 concentratioJI of impurities is lower thall in the case of a 31 process wllere the gate oxida~ion is done before the source and 4 1 drain cliffusions.
51 One kno~n technique for overcoming certain of the above 61 undesirable characteristics of the conventional CMOS technique 7¦ employs a silicon nitride (Si3N4) mask to define the openings 8 ! for the P+ and N~ source and drain diffusions, the silicon - ~ ;
g ¦ nitride mask also defining the gate area. After the source

10 ¦ and drain diffusion steps, the silicon nitride layer is

11 ¦ removed from all areas except the gate regions and a thick

12 ¦ silicon oxide layer is grown on all such areas, leaving the

13 ¦ silicon nitride over the sel-aligned gate areas. After the

14 ¦ thick oxide has been grown, the silicon nitride defining the I5 ¦ gate regions is selectively etched away and replaced by a thin 16 silicon oxide gate layer. Thereafter the contact openings are ~ -17 made in the thick oxide in the source and drain regions and a 18 metallization step forms the source and drain contacts and the 19 metal gate electrodes. In this self-aligning gate tecllnique 2~ there is no overlap of the thin gate oxide and the source and 21 -drain regions so that there is no parasitic capaci~ance of the 22 type described above. ~owever, due ~o the misalignment of ~he 23. P+ and N+ diffusion masks, the contact openings through the 24 thick oxide layer and into the P+ and N~ source and drain regions must be designed well within the boundaries of the 26 ¦ source and drain regions and tlle resulting area size for the 27 large scale CMOS structure is undesirably great. `~

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SU~IM~Y OF rEIE PRESENT INVENTION ;~ -The present invention provides a novel method whereby a self-aligned gate CMOS struc~ure i8 provided which employs no additional masking steps as compared to the standard C~IOS process but which provldes the advantages oE self-alignment between the N+ and P+ diffusions with respect to the gate area, contact openings which do not overlap the edge of the P~ or N-~ diffused areas independently of the amount `
of misalignment between the P+, N+ and contact opening masking levels, and a shallower junction depth than in the case of the conventional CMOS process.
In the method of the present invention used to form P channel and N channel gate devices on insulating substrates, a self-aligning gate technique is utilized and only five masking steps are employed. In this novel technique a silicon gate layer and an overlying silicon nitride layer are formed over the N type silicon layer grown on the insulating substrate. The first masking step is utiliz-ed to define the P+ source and drain regions which are the made in the N ~ ~
type grown silicon layer. After P+ diffusion, the second ; -masking step is utilized to define those areas where the grown silicon is etched to isolate the P channel regions in the grown silicon layer from the N channel regions. ~fter development of the photoresist, boron atoms are implanted in : -:
the N channel transistor area, the photoresist acting as a .
mask against the ion implantation. The oxide not protected by the photoresist is etched away and a silicon etch performed to isolate the various transistors. The silicon nitride : .',,: :~
still present over the N channel transistor masks this region against the silicon etch. Thereafter a third masking step is used to deflne the N+ diffusion regions in the grown silicon layer. After removal of the nitride layer still left over _ 5 _ ~vb/~J~
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the gate regions3 a fourth masking step then defines the contact openings to the P-~ drain and source regions and the N~ drain and source regions. A fifth masking step is then employed to define the metalli~ation areas for forming contact ~ ;
to the source and drain regions and for forming the gate electrodes over the gate regions. Since only five masking steps are employed in this novel technique for fabricatlng P channel and N channel devices in insulating substrates, ~ -one masking step is saved over the conventional CMOS fabrica~
tion technique described abovP. In addition, the conventional ~ -CMOS fabrication method for fabricating P and N channel -devices on insulating substrates employs a seventh masking step, i.e., a silicon etch mask, and therefore the present technique saves two masking steps over the known conventional CMOS technique employed on insulating substrates. ;

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..~.-BRIEF DESCRIPTION OF THE DRAWINGS
Figures 1 ~hro~lgh 6 lnclusive are cross-sectional views ill~lstrating six successive stages in the fabrication ',;, of a self-alignment gate type CMOS device of the present ~, .
invention.
. .` . , Figures 7 through ll inclusive are cross-sectional views illustrating certain successive stages in the fabrication "~ ,' , ,' ' of another form of self-alignment CMOS device on an insulating substrate utilizing the present invention and employing five , masking steps.
Figures 12 through 15 inclusive are cross-sectional views illustrating the successive stages in the fabrication .~
of a form of self-alignment gate type CMOS which is a modi- '' '' ' ~: .' . ' fication of the device of Figures 1 through 6. ' :
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Figures 16 through l9 inclusive are cross-sectional ~` , ,, ~ ,.
views illustrating the fabrication steps of a further form ''' ', of self-slignment CMOS device incorporatlng the present invention.
'DESCRIPTIO'N' OF'THE P'REFE'RRED EMBOD'IMENT .,`~
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-2`0 ~ Referring now to Figures 1 through 6, a semiconductor ,~

device made in accordance with the present invention is ~.
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shown in a preliminary fabrication stage~ in Figure 1 wherein ' the first masking and oxide etching stage has been employed ;
to form the desired openings 11 in the silicon oxide layer 12 formed on the N substrate 13 of the body, the P- regions ;~
14 being diffused into the N substrate 13 through said ' ,~
openings in well known manner. Ater the diffusion of the various P- regions 14, the silicon oxide layer 12 is stripped , from the surface and thereafter a thin silicon oxide gate layer 15, for example 1,000 angstroms, is formed over the ,~
entire surface.' This layer is then followed by the growth ~ ~ ' ,: . :' ' mb ~ 7 -1~5'7~

by standard techni~lues of a thin silicon nitride (Si3N4) mask layer 16 on the oxide layer 15, this silicon nitride layer 16 being about 1000-2000 A thick.
A second mask is then used to define the P+
diffusion regions, i.e., the P+ source and drain regions 17, 17' for the P channel devices and the P-~ guard rings 18 for the N channel regions to be subsequently formed in the P- regions 14. Openings in the silicon nitride layer ~ ' 16 and the silicon oxide layer 15 are then formed by ;
conventional etching to expose these P+ regions. A P+
diffusion then takes place to form the P+ regions 17, 17', 18 during which diffusion the thick silicon oxide layer 19 is formed over these P+ regions (see Fig.;2).
Thereafter a third masking step, subsequent silicon nitride etch and silicon oxide etch, and N+ diffusion are utili~ed to form the N+ diffusion regions 21~ 21~, 22 in the N substrate 13. During the diffusion a thick thermal ` `~
oxide 23 forms over these regions. This stage of fabrica-; ::
tion is shown in Fig. 3. The N+ regions 219 21~ form the ~:
N channel devices in the P- regions 14 and the N+ regions 22 for= isolation rings around the various P channel regions. ~ `

It should be understood that the P+ and N+ guard rings 18 and 22 are not necessary in all cases in the formation of :
P channel and N channel devices utilizing the present invention.
A fourth masking step is then employed to define ~ -. . .
the contact openings 24 through the thick silicon o~ide - ;

layers 19 and 22 to the P+ and N+ source and drain regions 17, 17' and 21, 21~ and a silicon oxide etch follows to - ~-remove the oxide at openings 24 (see Fig. 4 mb ~ 8 -,. ~

7'~15 ~ fifth masking step is then provided to protect all areas on the surface except the 8ate regions of the ; -P channel 17, 17' and N channel 21, 21' devices. A
silicon oxide etch is then used to remove any oxide film that may be on the Si3N4 layers at the gate region of the channels. This is followed by etching away the Si3N4 layer 16 at the gate regions of the P+ channel and N+
channel devices (see Fig. 5).
A sixth mask is then iormed over the surface of the device to define the metal contact 25 for the various source and drain regions and the gate electrodes 26 for the channel regions (see Fig. 6).
Due to the utilization of the silicon nitride mask layer 16 in ~he gate regions during the diffusion of - the source and drain regions 17l 17', 21, 21' in both the -~ ~6 j. , N channel devices and the P channel devices, the gate regions are self-aligned with regard to the edges of the diffused source and drain regions 17, 17',21, 21'. Thus ~ no parasitic capacitance is formed in these regions due to the fact that the metal of the gate electrode 26 is separated from the source and drain diffusion regions 17, 17', 21, 21' by a thick oxide layer as opposed to an overlapping thin oxide gate layer as in the conventional CNOS devices.
i, Also~the silicon nitride layer 16 at the outer edges of the P+ diffusion regions 179 17' and the N~
diffusion reglons 21, 21' acts as one boundary of the ~-mask for the contact openings 24 to be made in the thick oxide metal films 19 and 23. Thus, although the contact opening mask may extend beyond the edges of the regions m~/~ 9 , ~ :: - ,' , , , :, ~ . . . .

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17, 17' and 21, 21' due to misalignment or the llke, the silicon nitrlde layer 16 acts as an effactive etch ~ ~
defining mask for the contact opening. As a result, large ~ `
si~e CMOS structures can be limited in their overall area.
This novel fabricat~on technique uses a processing whlch i9 compatible with standard metal gate CMOS technology.
It utilizes the same number of masking steps, but the -~
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process steps for the P+ and N-~ diffusions are less critical, and higher density devices are produced.
It should be noted that the particular conductivity for the substrate 13 and regions 21, 21' is chosen as M
type and the conductivity for the regions 14 and 17, 17~
is chosen as P type. Devices with the opposite conductivity for these regions may be fabricated by the novel process described above.
Referring now to Figures 7 through 11 a novel ;
technique is disclosed wherein the self-aligning gate technique of the present invention is employed for the formation of P channel and N channel gate devices on an insulating substrate, this novel technique employing only ~;
five masking steps in the fabrication process. In accordance with standard insulating substrate techniques, a one-half to one micron thick N layer 31 in the form of single crystal ;
silicon is grown on the insulating substrate 32 which may be, for example, sapphire or spinel. A thin silicon oxide gate layer 33, for example 1000 A thick, is grown on the surface of the N silicon and a thin, for example 1000-2000 A thick, silicon nitride layer 34 is grown over the oxide layer.

mb~ ~ ~ - lO -1l)~7~L5 - A first masking step followed by a silicon nitride Ptch and a silicon oxide etch is used to open the surface layers to the P+ diffuæion regions and the P+ regions 35 are formed therein by diEfusion. During the diffusion ~;
step, a thick silicon oxide layer 36 forms over these regions. The gate regions between the source and drain P~ diffusion regions 35 are then protected by a photoresist mask 37, this mask 37 and the silicon nitride layer 34 over the remainder of the surface of the device protecting the ~-silicon oxide at all regions except where openings 38 are desired in the silicon oxide and in the underlying N
silicon layer forming isolation regions between the P
channel devices and the N channel devices. Thereafter ;~
a well known P- ion implantation step is utilized to form a P- channel region 39 between-the source and drain region l -areas of the to be formed N channel devices. An oxide etch followed by a silicon etch is then utilized to remove -the portion of the silicon oxide layer 36 and the silicon layer 31 in regions 38. The photoresist 37 protects the - : ;
~20 P channel devices on the substrate 32 during etching while the silicon nitride layer 34 protects the N channel regions on the substrate 32.
A thermal oxide is then grown over the substrate to cover the edges 41 of the P channeI regions and the N ~ ~
channel regions. A third mask is then formed to define ~ :
the N+ diffusion regions 42 and the silicon nitride layer -and underlying silicon oxide layer are etched away from these regions, the N+ diffusion then taking place to form the N+ source and drain regions 42 in the N channel devices (Fig. 10). During this N+ diffusion a thick thermal oxide layer 43 is grown over the N+ regions.
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A ~ourtll m~sk is then formed over the device to define the openings Ln the thick oxide layers 36 and 43 leading to the various P+ and N+ source and drain regions and an oxide etch produces these openings. Then a silicon nitride etch, such as a hot phosphoric etchant, is used to etch away the silicon nitride layer 34 remainlng at the gate regions. The fifth masking step is then employed to define the metallization regions where the metal contacts 44 are formed with the various source and drain regions `
and the gate electrodes 45 are formed at the gate reglons.
It is noted that in this embodiment the silicon .
nitride layer 34 acts as a mask for the self-aligning gate in the P and N channel devices. In addition, a portion of t~te silicon nitride layer also serves to define the isolation region 38 made in the grown silicon layer 31 between the N channel devices and the P channel devices.
This novel process uses standard CMOS fabrication techniques while providing self-aligned gate devices with a five mask process. The standard non-self-aligned CMOS technique 20 ~ used to form devices on insulated substrates heretofore ` ;
utili2ed seven masking steps in the processing; thus the present invention contributes a saving in the number of masking steps required.
When the process described in Figs. 1-6 above is employed, at the end of the process all the undiffused regions are protected with a layer of silicon nitride 16 over thin gate oxide 15 except at the gate regions of the devices. Sometimes this is an undesirable configuration, because of the low field inversion voltage of the layer of silicon nitride over gate oxide.

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This problem can be eliminated by modifying the process flow described above for Figs. 1-6 in the following manner as shown in Figs. 12-15. The first operation is the growth of a thin gate oxide layer 15 followed by a sillcon nitride deposition layer 16. With the first mask the sillcon nitride 16 and oxide 15 are removed in all the regions where no diffusions are wanted at the end of the process, and are therefore left where source, drain, ~-gate regions and guard rings are wanted (see Fig. 12~.
During the second masking operation, a negative "; ~
photoresist 51 is deposited and exposed in such a way that, ~ ;
after development, the photoresist is left only outside the regions when an N channel transistor will be formed.
By means of the well known ion implantation process, a controlled amount of boron atoms 52 are introduced into the silicon at the N channel transistor region to form a shallow layer 14~ (see Fig. 12); the photoresist 51 where present prevents the boron atoms from reachlng the silicon substrate 13. The implanted boron atoms are then driven 20~ in to form ehe P- region 14 and at the end of this diffusion step a thick thermal oxide 53 is grown selectively in the regians not protected by the silicon nitride layer 16 (Fig. 13). ~
The third masking and etching step removes the silicon nitride 16 and gate oxide 15 from the P channel source and drain regions 17, 17' and guard region 18 and the P+ diffusion is performed. The fourth masking step opens the N channel source and drain regions 21, 21' and guard region 22 after which the N~ diffusion is performed (Fig. 14). The silicon nitride 16 is then removed at the m ~ 13 -c .- - :. . : . : :, . . .

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gate regions with a selective etch of phosphoric acid.
The fifth masking operation is used to form contact openings to the source and drain regions and, aftcr metallization, the sixth mask defines the metal inter-connect pattern 25, 26 (Fig. 15).
When this process is used, the self-aligning nature of the formation of the gate regions is retained and also the contact openings to the source and drain regions are limited to the edges of such regions because the initial oxide grown outside the diffused regions can be made easily at least two times thicker than the oxide ~-~
grown during N+ and P+ diffusions.
It is well known that if a CMOS circuit is operated ~ / `
with a low supply voltage (e.g., below 5 volts), the P+ and `~ ~`
N~ guard rings can be used in direct contact to the source- ~ ~
~. 1`.' :,, drain diffus~on edges and no undiffused spacing has to be left beeween the guard rings themselves.

The present invention can be applied to fabricate such circuits as shown in Figs. 16-19 inclusive with the 20significant advantage that only five masking steps are now ~ ;
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needed and the self-aligned nature of the gate formatio~
is retained.
As shown in Fig. 16, after formation of gate oxidation layer 15 and nitride deposition layer 169 the N+ source and drain regions 21, 21' are defined with the first masking operation together with the N+ guard ring region 22 around the P channel transistor and the silicon nitride etched . .
at these regions.

During the second masking operation photoresist 51 is used to mask the thin layer 14' of implanted boron atoms .~
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. : , 52 outside the N channel transistor area and the step of ion implantation is carried out followed by resist removal.
After drive in of the shallow implanted boron layer to form region 14, the thin gate oxide 15 is removed wherever it is exposed and the N+ diffusion 21, 21' and 22 performed (Fig. 17).
The third mask is then used to remove the nitride . - . ., , ~
and gate oxide from the P+ region 17, 17' and 18. After P~ diffusion (Fig. 18), the nitride 16 left on the gate areas is then selectively removed. Contact holes to the source-drain regions are opened with the fourth masking operation. Metallization takes place and then the fifth i mask is then used to define the metal pattern (Fig. 19).
Again, since the oxide grown after N+ diffusion . .
can be made much thicker than the gate oxide, the third mask openings can overlap the already diffused N+ regions, but still the P+ diffusion will be exactly coincident `
with the N~ diffusion. ~ ;
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For the three processes described in Figs. 1-6, 12-15 and 16-19, a process variation can be introduced with considerable advantage for the alignment of the contact mask to the diffused regions and the metal mask to the gate -~
regions. Instead of defining the P+ and N+ source-drain regions with two separate masking steps, both regions may be defined with one masking operation in accordance with the well known method of diffusion from doped oxide. After a layer of oxide heavily doped with phosphorus is deposited `
on the wafer surface with a subsequent mask, the doped oxide is removed from the P+ regions. A P+ predeposition is then performed, the doped oxide removed, and thermal oxide grown over the diffused regions.

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Claims (3)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. The method for manufacture of a silicon semiconductor device comprising the steps of:
forming a first semiconductor layer of a first con-ductivity type over the surface of an insulating substrate, forming an oxide layer over the surface of said first semiconductor layer, forming a silicon nitride layer over the surface of said oxide layer, masking and etching said silicon nitride and said oxide layer to form openings therein at first regions of said first semiconductor layer, diffusing a dopant through said latter openings to form source and drain regions of said second conductivity type in said first regions of said first semiconductor layer with a gate region extending between the source and drain regions, a thick oxide layer being formed over said source and drain regions during said diffusion, masking said gate region and a portion of the oxide layer at the source and drain regions adjacent said gate region, forming a thin layer channel region of a second con-ductivity type in a second region of said first semiconductor layer removed from said first region, etching both the thick oxide layer and the underlying first semiconductor layer in the outer portions of said first region to isolate the diffused source and drain regions in said first region of said first semiconductor layer from said second region of said first semiconductor layer,
1. claim 1 continued.....
   
   forming an insulating oxide layer over the exposed surfaces of said first semiconductor layer, and simultaneously driving said thin layer channel region into said first semi-conductor layer, masking and etching openings through said silicon nitride layer and said underlying silicon oxide layer to define source and drain regions separated by a gate region in said second region of said first semiconductor layer, diffusing a dopant through said latter openings to form source and drain regions in said second region of said first semiconductor layer, masking and etching openings in the oxide layer over said source and drain regions in said first and second regions of said first semiconductor layer to form connect openings thereto, etching away the silicon nitride layer remaining over the gate regions, depositing a metallization layer over the device, masking said metal layer to define the metal connect and interconnect regions for the various source, drain, and gate regions, and etching the metal to form the gate electrodes and the source and drain connects.
2. 2. The method as claimed in claim 1 wherein the step of forming the channel region of a second conductivity type comprises the ion implantation of the dopant in said second region of the first semiconductor layer.
3. 3. The method as claimed in claim 1 wherein said first conductivity type is N type and said second conductivity type is P type.