CA1057415A - Procede de fabrication de dispositifs cmos avec autoreperage des couches semiconductrices - Google Patents

Procede de fabrication de dispositifs cmos avec autoreperage des couches semiconductrices

Info

Publication number
CA1057415A
CA1057415A CA317,206A CA317206A CA1057415A CA 1057415 A CA1057415 A CA 1057415A CA 317206 A CA317206 A CA 317206A CA 1057415 A CA1057415 A CA 1057415A
Authority
CA
Canada
Prior art keywords
regions
layer
gate
source
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA317,206A
Other languages
English (en)
Inventor
Gregorio Spadea
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/575,655 external-priority patent/US3983620A/en
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Priority to CA317,206A priority Critical patent/CA1057415A/fr
Application granted granted Critical
Publication of CA1057415A publication Critical patent/CA1057415A/fr
Expired legal-status Critical Current

Links

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
CA317,206A 1975-05-08 1978-12-01 Procede de fabrication de dispositifs cmos avec autoreperage des couches semiconductrices Expired CA1057415A (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA317,206A CA1057415A (fr) 1975-05-08 1978-12-01 Procede de fabrication de dispositifs cmos avec autoreperage des couches semiconductrices

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US05/575,655 US3983620A (en) 1975-05-08 1975-05-08 Self-aligned CMOS process for bulk silicon and insulating substrate device
CA246,453A CA1057862A (fr) 1975-05-08 1976-02-24 Methode de fabrication de cmos a auto-alignement pour dispositif au silicium et a substrat isolant
CA317,206A CA1057415A (fr) 1975-05-08 1978-12-01 Procede de fabrication de dispositifs cmos avec autoreperage des couches semiconductrices

Publications (1)

Publication Number Publication Date
CA1057415A true CA1057415A (fr) 1979-06-26

Family

ID=27164348

Family Applications (1)

Application Number Title Priority Date Filing Date
CA317,206A Expired CA1057415A (fr) 1975-05-08 1978-12-01 Procede de fabrication de dispositifs cmos avec autoreperage des couches semiconductrices

Country Status (1)

Country Link
CA (1) CA1057415A (fr)

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