SE9704209L - Semiconductor components and manufacturing process for semiconductor components - Google Patents

Semiconductor components and manufacturing process for semiconductor components

Info

Publication number
SE9704209L
SE9704209L SE9704209A SE9704209A SE9704209L SE 9704209 L SE9704209 L SE 9704209L SE 9704209 A SE9704209 A SE 9704209A SE 9704209 A SE9704209 A SE 9704209A SE 9704209 L SE9704209 L SE 9704209L
Authority
SE
Sweden
Prior art keywords
semiconductor components
acceptor
type impurities
gettering
layer
Prior art date
Application number
SE9704209A
Other languages
Unknown language ( )
Swedish (sv)
Other versions
SE9704209D0 (en
Inventor
Anders Soederbaerg
Haakan Sjoedin
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE9704209A priority Critical patent/SE9704209L/en
Publication of SE9704209D0 publication Critical patent/SE9704209D0/en
Priority to TW87100709A priority patent/TW396434B/en
Priority to PCT/SE1998/002063 priority patent/WO1999026291A2/en
Priority to AU12678/99A priority patent/AU1267899A/en
Publication of SE9704209L publication Critical patent/SE9704209L/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

A semiconductor component is disclosed, having a device layer comprising at least one lateral insulating area, such as a trench, the walls of said lateral insulating area being covered with a gettering layer functioning as a getter when processing the semiconductor component. Preferably, the gettering layer is substantially without acceptor and/or donor type impurities, or the concentration of acceptor and/or donor type impurities is not greater than the concentration of acceptor and/or donor type impurities in the trench wall. The gettering layer comprises a gettering material such as polysilicon or porous silicon, or a silicide, and is covered with a layer of an insulating material. A method for the manufacturing of such a component is also disclosed.
SE9704209A 1997-11-17 1997-11-17 Semiconductor components and manufacturing process for semiconductor components SE9704209L (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
SE9704209A SE9704209L (en) 1997-11-17 1997-11-17 Semiconductor components and manufacturing process for semiconductor components
TW87100709A TW396434B (en) 1997-11-17 1998-01-20 Semiconductor device and manufacturing method for semiconductor devices
PCT/SE1998/002063 WO1999026291A2 (en) 1997-11-17 1998-11-16 Semiconductor component and manufacturing method for semiconductor components
AU12678/99A AU1267899A (en) 1997-11-17 1998-11-16 Semiconductor component and manufacturing method for semiconductor components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9704209A SE9704209L (en) 1997-11-17 1997-11-17 Semiconductor components and manufacturing process for semiconductor components

Publications (2)

Publication Number Publication Date
SE9704209D0 SE9704209D0 (en) 1997-11-17
SE9704209L true SE9704209L (en) 1999-05-18

Family

ID=20409013

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9704209A SE9704209L (en) 1997-11-17 1997-11-17 Semiconductor components and manufacturing process for semiconductor components

Country Status (4)

Country Link
AU (1) AU1267899A (en)
SE (1) SE9704209L (en)
TW (1) TW396434B (en)
WO (1) WO1999026291A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000353797A (en) * 1999-06-11 2000-12-19 Mitsubishi Electric Corp Semiconductor wafer and manufacture thereof
US20020140030A1 (en) * 2001-03-30 2002-10-03 Mandelman Jack A. SOI devices with integrated gettering structure
US6958264B1 (en) 2001-04-03 2005-10-25 Advanced Micro Devices, Inc. Scribe lane for gettering of contaminants on SOI wafers and gettering method
JP2004172362A (en) * 2002-11-20 2004-06-17 Hyogo Prefecture Impurity removing method in semiconductor wafer, the semiconductor wafer, and semiconductor device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5110752A (en) * 1991-07-10 1992-05-05 Industrial Technology Research Institute Roughened polysilicon surface capacitor electrode plate for high denity dram
US5430315A (en) * 1993-07-22 1995-07-04 Rumennik; Vladimir Bi-directional power trench MOS field effect transistor having low on-state resistance and low leakage current
JPH07273121A (en) * 1994-03-31 1995-10-20 Toshiba Corp Fabrication of semiconductor device
US5478758A (en) * 1994-06-03 1995-12-26 At&T Corp. Method of making a getterer for multi-layer wafers
US5646053A (en) * 1995-12-20 1997-07-08 International Business Machines Corporation Method and structure for front-side gettering of silicon-on-insulator substrates

Also Published As

Publication number Publication date
WO1999026291A2 (en) 1999-05-27
AU1267899A (en) 1999-06-07
WO1999026291A3 (en) 1999-08-05
TW396434B (en) 2000-07-01
SE9704209D0 (en) 1997-11-17

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Legal Events

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