SE9600854D0 - Production of signal processors using behavioral models - Google Patents

Production of signal processors using behavioral models

Info

Publication number
SE9600854D0
SE9600854D0 SE9600854A SE9600854A SE9600854D0 SE 9600854 D0 SE9600854 D0 SE 9600854D0 SE 9600854 A SE9600854 A SE 9600854A SE 9600854 A SE9600854 A SE 9600854A SE 9600854 D0 SE9600854 D0 SE 9600854D0
Authority
SE
Sweden
Prior art keywords
processor
layout
signal processors
description
units
Prior art date
Application number
SE9600854A
Other languages
English (en)
Other versions
SE9600854L (sv
SE505783C2 (sv
SE505783C3 (sv
Inventor
Roejaas Karl-Gunnar Andersson
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Publication of SE9600854L publication Critical patent/SE9600854L/xx
Priority claimed from SE9503432A external-priority patent/SE9503432D0/sv
Priority to SE9600854A priority Critical patent/SE505783C3/sv
Publication of SE9600854D0 publication Critical patent/SE9600854D0/sv
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to AU72331/96A priority patent/AU7233196A/en
Priority to CNB961985186A priority patent/CN1147813C/zh
Priority to EP96933702A priority patent/EP0853792B1/en
Priority to CA002233843A priority patent/CA2233843A1/en
Priority to ES96933702T priority patent/ES2191768T3/es
Priority to JP9514195A priority patent/JPH11513512A/ja
Priority to PCT/SE1996/001236 priority patent/WO1997013209A1/en
Priority to KR10-1998-0702488A priority patent/KR100371667B1/ko
Priority to DE69626029T priority patent/DE69626029T2/de
Publication of SE505783C2 publication Critical patent/SE505783C2/sv
Publication of SE505783C3 publication Critical patent/SE505783C3/sv

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
SE9600854A 1995-10-03 1996-03-05 Foerfarande foer att tillverka en digital signalprocessor SE505783C3 (sv)

Priority Applications (10)

Application Number Priority Date Filing Date Title
SE9600854A SE505783C3 (sv) 1995-10-03 1996-03-05 Foerfarande foer att tillverka en digital signalprocessor
DE69626029T DE69626029T2 (de) 1995-10-03 1996-10-02 Verfahren zum herstellen eines digitalen signalprozessors
KR10-1998-0702488A KR100371667B1 (ko) 1995-10-03 1996-10-02 디지털신호프로세서를제조하는방법
AU72331/96A AU7233196A (en) 1995-10-03 1996-10-02 Method of producing a digital signal processor
PCT/SE1996/001236 WO1997013209A1 (en) 1995-10-03 1996-10-02 Method of producing a digital signal processor
CNB961985186A CN1147813C (zh) 1995-10-03 1996-10-02 生产数字信号处理器的方法
EP96933702A EP0853792B1 (en) 1995-10-03 1996-10-02 Method of producing a digital signal processor
CA002233843A CA2233843A1 (en) 1995-10-03 1996-10-02 Method of producing a digital signal processor
ES96933702T ES2191768T3 (es) 1995-10-03 1996-10-02 Procedimiento de produccion de un procesador de señales numericas.
JP9514195A JPH11513512A (ja) 1995-10-03 1996-10-02 ディジタル信号プロセッサの製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9503432A SE9503432D0 (sv) 1995-10-03 1995-10-03 Production of signal processors using behavioral models
SE9600854A SE505783C3 (sv) 1995-10-03 1996-03-05 Foerfarande foer att tillverka en digital signalprocessor

Publications (4)

Publication Number Publication Date
SE9600854L SE9600854L (sv)
SE9600854D0 true SE9600854D0 (sv) 1996-03-05
SE505783C2 SE505783C2 (sv) 1997-10-06
SE505783C3 SE505783C3 (sv) 1997-10-06

Family

ID=26662390

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9600854A SE505783C3 (sv) 1995-10-03 1996-03-05 Foerfarande foer att tillverka en digital signalprocessor

Country Status (10)

Country Link
EP (1) EP0853792B1 (sv)
JP (1) JPH11513512A (sv)
KR (1) KR100371667B1 (sv)
CN (1) CN1147813C (sv)
AU (1) AU7233196A (sv)
CA (1) CA2233843A1 (sv)
DE (1) DE69626029T2 (sv)
ES (1) ES2191768T3 (sv)
SE (1) SE505783C3 (sv)
WO (1) WO1997013209A1 (sv)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9814015D0 (en) * 1998-06-29 1998-08-26 Sgs Thomson Microelectronics Design of an application specific processor (ASP)
GB9814017D0 (en) 1998-06-29 1998-08-26 Sgs Thomson Microelectronics Design of an application specific processor (ASP)
GB9814014D0 (en) 1998-06-29 1998-08-26 Sgs Thomson Microelectronics Design of an application specific processor (ASP)
KR20010104622A (ko) * 1998-10-14 2001-11-26 추후기재 반도체 설계의 구성 및 기능을 관리하는 방법 및 장치
US6862563B1 (en) 1998-10-14 2005-03-01 Arc International Method and apparatus for managing the configuration and functionality of a semiconductor design
EP1351154A2 (en) 1998-11-20 2003-10-08 Altera Corporation Reconfigurable programmable logic device computer system
GB9828381D0 (en) * 1998-12-22 1999-02-17 Isis Innovation Hardware/software codesign system
FR2787597B1 (fr) 1998-12-22 2001-01-26 St Microelectronics Sa Procede de conception d'un coeur de microprocesseur
WO2000046704A2 (en) * 1999-02-05 2000-08-10 Tensilica, Inc. Automated processor generation system and method for designing a configurable processor
US6477697B1 (en) 1999-02-05 2002-11-05 Tensilica, Inc. Adding complex instruction extensions defined in a standardized language to a microprocessor design to produce a configurable definition of a target instruction set, and hdl description of circuitry necessary to implement the instruction set, and development and verification tools for the instruction set
WO2000070446A2 (en) * 1999-05-13 2000-11-23 Arc International U.S. Holdings Inc. Method and apparatus for loose register encoding within a pipelined processor
US6560754B1 (en) 1999-05-13 2003-05-06 Arc International Plc Method and apparatus for jump control in a pipelined processor
WO2001069411A2 (en) 2000-03-10 2001-09-20 Arc International Plc Memory interface and method of interfacing between functional entities
US7051189B2 (en) 2000-03-15 2006-05-23 Arc International Method and apparatus for processor code optimization using code compression
JP2002049652A (ja) * 2000-08-03 2002-02-15 Hiroshi Yasuda デジタル回路設計方法、そのコンパイラーおよびシミュレータ
US7343594B1 (en) 2000-08-07 2008-03-11 Altera Corporation Software-to-hardware compiler with symbol set inference analysis
EP1356401A2 (en) 2000-08-07 2003-10-29 Altera Corporation Software-to-hardware compiler
EP1191443A3 (en) 2000-09-22 2004-03-03 International Business Machines Corporation Method and system for testing a processor
AU2003223746A1 (en) 2002-04-25 2003-11-10 Arc International Apparatus and method for managing integrated circuit designs
US7278122B2 (en) * 2004-06-24 2007-10-02 Ftl Systems, Inc. Hardware/software design tool and language specification mechanism enabling efficient technology retargeting and optimization
CN100373388C (zh) * 2005-09-16 2008-03-05 北京中星微电子有限公司 一种快速生成逻辑电路的方法
US8127113B1 (en) 2006-12-01 2012-02-28 Synopsys, Inc. Generating hardware accelerators and processor offloads
US8156457B2 (en) * 2009-09-24 2012-04-10 Synopsys, Inc. Concurrent simulation of hardware designs with behavioral characteristics
KR101849702B1 (ko) 2011-07-25 2018-04-17 삼성전자주식회사 외부 인트린직 인터페이스
US8959469B2 (en) 2012-02-09 2015-02-17 Altera Corporation Configuring a programmable device using high-level language
US9250900B1 (en) 2014-10-01 2016-02-02 Cadence Design Systems, Inc. Method, system, and computer program product for implementing a microprocessor with a customizable register file bypass network

Also Published As

Publication number Publication date
CA2233843A1 (en) 1997-04-10
AU7233196A (en) 1997-04-28
EP0853792B1 (en) 2003-01-29
EP0853792A1 (en) 1998-07-22
CN1202972A (zh) 1998-12-23
SE9600854L (sv)
JPH11513512A (ja) 1999-11-16
SE505783C2 (sv) 1997-10-06
KR100371667B1 (ko) 2003-03-28
CN1147813C (zh) 2004-04-28
KR19990064011A (ko) 1999-07-26
SE505783C3 (sv) 1997-10-06
WO1997013209A1 (en) 1997-04-10
DE69626029D1 (de) 2003-03-06
DE69626029T2 (de) 2003-09-25
ES2191768T3 (es) 2003-09-16

Similar Documents

Publication Publication Date Title
SE9600854D0 (sv) Production of signal processors using behavioral models
US5615124A (en) Autonomous evolution type hardware design system
US20030023950A1 (en) Methods and apparatus for deep embedded software development
US6263303B1 (en) Simulator architecture
WO2000022553A3 (en) Method and apparatus for managing the configuration and functionality of a semiconductor design
Parasch et al. Development and application of a designer oriented cyclic simulator
Chu et al. Three decades of HDLs. I. CDL through TI-HDL
JP2792902B2 (ja) ラフ・シミュレーション装置
Dall'Ora et al. Verilog-a implementation of generic defect templates for analog fault injection
WO2002063473A1 (fr) Procede de developpement d'un systeme de traitement de donnees et tableau d'evaluation
Jain et al. Mapping switch-level simulation onto gate-level hardware accelerators
CN114550302A (zh) 生成动作序列的方法及装置、训练相关模型的方法及装置
Dettmer Formal chip design-a functional approach
JPS63211467A (ja) 回路構成復元方式
JPH04333171A (ja) シミュレーション装置
JPH027171A (ja) 論理回路合成方式
Wahab et al. High-level design methodology for the implementation of image processing ASICs
JPH09251483A (ja) セルライブラリ作成方法
JPS63228229A (ja) 図的言語処理システム
Ip et al. Digital signal processing system design methodology
Fujita Application of temporal logic to the assistance of hardware logic design
Pehrson An interactive framework for design automation
Pichler CAST—Modelling Approaches in Software Design
Dowsing et al. A framework for the synthesis of hardware from occam
JPH0682523A (ja) 論理回路シミュレーションのサイクルテストデータの変換方法

Legal Events

Date Code Title Description
NUG Patent has lapsed