WO2000022553A3 - Method and apparatus for managing the configuration and functionality of a semiconductor design - Google Patents

Method and apparatus for managing the configuration and functionality of a semiconductor design Download PDF

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Publication number
WO2000022553A3
WO2000022553A3 PCT/IB1999/002030 IB9902030W WO0022553A3 WO 2000022553 A3 WO2000022553 A3 WO 2000022553A3 IB 9902030 W IB9902030 W IB 9902030W WO 0022553 A3 WO0022553 A3 WO 0022553A3
Authority
WO
WIPO (PCT)
Prior art keywords
design
hdl
managing
functionality
configuration
Prior art date
Application number
PCT/IB1999/002030
Other languages
French (fr)
Other versions
WO2000022553A2 (en
Inventor
James Hakewill
Mohammed Khan
Original Assignee
Arc Cores Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Arc Cores Ltd filed Critical Arc Cores Ltd
Priority to AU15811/00A priority Critical patent/AU1581100A/en
Priority to KR1020017004710A priority patent/KR20010104622A/en
Priority to EP99958445A priority patent/EP1121656A2/en
Priority to IL14234299A priority patent/IL142342A/en
Publication of WO2000022553A2 publication Critical patent/WO2000022553A2/en
Publication of WO2000022553A3 publication Critical patent/WO2000022553A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Abstract

A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating 'makefiles' for purposes of simulation and/or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed.
PCT/IB1999/002030 1998-10-14 1999-10-14 Method and apparatus for managing the configuration and functionality of a semiconductor design WO2000022553A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU15811/00A AU1581100A (en) 1998-10-14 1999-10-14 Method and apparatus for managing the configuration and functionality of a semiconductor design
KR1020017004710A KR20010104622A (en) 1998-10-14 1999-10-14 Method and Apparatus for managing the configuration and functionality of a semiconductor design
EP99958445A EP1121656A2 (en) 1998-10-14 1999-10-14 Method and apparatus for managing the configuration and functionality of a semiconductor design
IL14234299A IL142342A (en) 1998-10-14 1999-10-14 Method and apparatus for managing the configuration and functionality of a semiconductor design

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10427198P 1998-10-14 1998-10-14
US60/104,271 1998-10-14

Publications (2)

Publication Number Publication Date
WO2000022553A2 WO2000022553A2 (en) 2000-04-20
WO2000022553A3 true WO2000022553A3 (en) 2000-08-10

Family

ID=22299556

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB1999/002030 WO2000022553A2 (en) 1998-10-14 1999-10-14 Method and apparatus for managing the configuration and functionality of a semiconductor design

Country Status (5)

Country Link
EP (1) EP1121656A2 (en)
KR (1) KR20010104622A (en)
AU (1) AU1581100A (en)
IL (1) IL142342A (en)
WO (1) WO2000022553A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7325221B1 (en) * 2000-08-08 2008-01-29 Sonics, Incorporated Logic system with configurable interface
JP2002230065A (en) 2001-02-02 2002-08-16 Toshiba Corp System lsi developing device and method
KR100818826B1 (en) 2002-04-25 2008-04-01 에이알씨 인터내셔널 A computerized apparatus for generating a design of an integrated circuit and a method for generating a hierarchy within an integrated circuit design having a plurality of components
US20050049843A1 (en) * 2003-08-29 2005-03-03 Lee Hewitt Computerized extension apparatus and methods
DE102004044963A1 (en) * 2004-09-16 2006-04-06 Tatung Co., Ltd. Agreement method for duplication use of hardware module on system-on-chip, involves calling related software function to output response data as execution result of hardware module, based on parameter requirement of hardware module
US8156457B2 (en) * 2009-09-24 2012-04-10 Synopsys, Inc. Concurrent simulation of hardware designs with behavioral characteristics
KR101635610B1 (en) * 2015-05-15 2016-07-05 주식회사 휴윈 Apparatus and method for analysis of pcb em and circuits
US10678975B2 (en) * 2017-11-07 2020-06-09 Amazon Tecnnologies, Inc. Code module selection for device design

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997013209A1 (en) * 1995-10-03 1997-04-10 Telefonaktiebolaget L M Ericsson (Publ) Method of producing a digital signal processor
US5812416A (en) * 1996-07-18 1998-09-22 Lsi Logic Corporation Integrated circuit design decomposition

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997013209A1 (en) * 1995-10-03 1997-04-10 Telefonaktiebolaget L M Ericsson (Publ) Method of producing a digital signal processor
US5812416A (en) * 1996-07-18 1998-09-22 Lsi Logic Corporation Integrated circuit design decomposition

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
BEREKOVIC M ET AL: "A core generator for fully synthesizable and highly parameterizable RISC-cores for system-on-chip designs", 1998 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS. SIPS 98. DESIGN AND IMPLEMENTATION (CAT. NO.98TH8374), 1998 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS. SIPS 98. DESIGN AND IMPLEMENTATION, CAMBRIDGE, MA, USA, 8-10 OCT. 1998, 1998, New York, NY, USA, IEEE, USA, pages 561 - 568, XP002137267, ISBN: 0-7803-4997-0 *
ELMS A: "Tuning a customisable RISC core for DSP", ELECTRONIC PRODUCT DESIGN, SEPT. 1997, IML TECHPRESS, UK, vol. 18, no. 9, pages 19 - 20, 22, XP000909039, ISSN: 0263-1474 *
JIN-HYUK YANG ET AL: "MetaCore: a configurable & instruction-level extensible DSP core", PROCEEDINGS OF THE ASP-DAC '98 ASIAN AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1998 (CAT. NO.98EX121), PROCEEDINGS OF 1998 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, YOKOHAMA, JAPAN, 10-13 FEB. 1998, 1998, New York, NY, USA, IEEE, USA, pages 325 - 326, XP002137268, ISBN: 0-7803-4425-1 *

Also Published As

Publication number Publication date
IL142342A (en) 2005-12-18
WO2000022553A2 (en) 2000-04-20
AU1581100A (en) 2000-05-01
IL142342A0 (en) 2002-03-10
KR20010104622A (en) 2001-11-26
EP1121656A2 (en) 2001-08-08

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