SE7810736L - Digital faslast slinga - Google Patents

Digital faslast slinga

Info

Publication number
SE7810736L
SE7810736L SE7810736A SE7810736A SE7810736L SE 7810736 L SE7810736 L SE 7810736L SE 7810736 A SE7810736 A SE 7810736A SE 7810736 A SE7810736 A SE 7810736A SE 7810736 L SE7810736 L SE 7810736L
Authority
SE
Sweden
Prior art keywords
pct
date
loop
addition circuit
circuit
Prior art date
Application number
SE7810736A
Other languages
Unknown language ( )
English (en)
Other versions
SE414104B (sv
Inventor
J S Hedin
G A Jarnestedt
Original Assignee
Ellemtel Utvecklings Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ellemtel Utvecklings Ab filed Critical Ellemtel Utvecklings Ab
Priority to SE7810736A priority Critical patent/SE414104B/sv
Priority to FI792894A priority patent/FI67004C/sv
Priority to DE19792953215 priority patent/DE2953215A1/de
Priority to PCT/SE1979/000205 priority patent/WO1980000904A1/en
Priority to NO793303A priority patent/NO148730C/no
Priority to US06/196,053 priority patent/US4360926A/en
Publication of SE7810736L publication Critical patent/SE7810736L/sv
Priority to DK253180A priority patent/DK149380C/da
Publication of SE414104B publication Critical patent/SE414104B/sv

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0066—Detection of the synchronisation error by features other than the received signal transition detection of error based on transmission code rule
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
  • Circuits Of Receivers In General (AREA)
  • Holo Graphy (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
SE7810736A 1978-10-13 1978-10-13 Digital faslast slinga SE414104B (sv)

Priority Applications (7)

Application Number Priority Date Filing Date Title
SE7810736A SE414104B (sv) 1978-10-13 1978-10-13 Digital faslast slinga
FI792894A FI67004C (fi) 1978-10-13 1979-09-18 Digital faslaost slinga
DE19792953215 DE2953215A1 (de) 1978-10-13 1979-10-12 Digital phase-locked loop
PCT/SE1979/000205 WO1980000904A1 (en) 1978-10-13 1979-10-12 Digital phase-locked loop
NO793303A NO148730C (no) 1978-10-13 1979-10-12 Digital faselaast sloeyfe
US06/196,053 US4360926A (en) 1978-10-13 1979-10-12 Digital phase-locked loop
DK253180A DK149380C (da) 1978-10-13 1980-06-12 Digital faselaast slaejfe

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE7810736A SE414104B (sv) 1978-10-13 1978-10-13 Digital faslast slinga

Publications (2)

Publication Number Publication Date
SE7810736L true SE7810736L (sv) 1980-04-14
SE414104B SE414104B (sv) 1980-07-07

Family

ID=20336100

Family Applications (1)

Application Number Title Priority Date Filing Date
SE7810736A SE414104B (sv) 1978-10-13 1978-10-13 Digital faslast slinga

Country Status (6)

Country Link
US (1) US4360926A (sv)
DK (1) DK149380C (sv)
FI (1) FI67004C (sv)
NO (1) NO148730C (sv)
SE (1) SE414104B (sv)
WO (1) WO1980000904A1 (sv)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4570130A (en) * 1982-10-20 1986-02-11 International Business Machines Corporation Input controller circuit apparatus for phase lock loop voltage controlled oscillator
US4930142A (en) * 1988-12-06 1990-05-29 Stac, Inc. Digital phase lock loop
DE69132247T2 (de) * 1990-03-14 2000-12-21 Alcatel, Paris Phasenverriegelte Schleifenanordnung
US5162910A (en) * 1990-10-03 1992-11-10 Thomson Consumer Electronics, Inc. Synchronizing circuit
AU2155292A (en) * 1991-05-21 1992-12-30 Elf Technologies, Inc. Methods and systems of preparing extended length flexible harnesses
US5442315A (en) * 1993-07-27 1995-08-15 International Business Machines Corporation Bit stream rate asynchronous digital phase-locked loop
DE19717642A1 (de) * 1997-04-25 1998-11-05 Siemens Ag Verfahren zur Datenregeneration
JP2001076437A (ja) 1999-09-06 2001-03-23 Victor Co Of Japan Ltd クロック信号発生装置
EP1231748B1 (de) * 2001-02-09 2004-10-06 Siemens Aktiengesellschaft Verfahren und Anordnung zur Regelung der Entscheiderschwelle und der Abtasttaktphase eines Datenregenerators für ein binäres Signal
DE10156111A1 (de) * 2001-11-16 2003-06-05 Philips Intellectual Property Empfangsschaltung zum Empfang von Nachrichtensignalen
US11511716B2 (en) * 2019-06-12 2022-11-29 Bendix Commercial Vehicle Systems Llc EBS tractor control line to trailer system to improve transmission timing for an air brake system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3355549A (en) * 1963-11-27 1967-11-28 Ortronix Inc Universal repeater
GB1477675A (en) * 1973-09-08 1977-06-22 Sony Corp Radio receivers with a phase locked loop as a demodulator
CA1063719A (en) * 1975-04-28 1979-10-02 Control Data Corporation Phase locked loop decoder
US4030045A (en) * 1976-07-06 1977-06-14 International Telephone And Telegraph Corporation Digital double differential phase-locked loop
FR2361019A1 (fr) * 1976-08-04 1978-03-03 Cit Alcatel Dispositif de decodage d'un message en code dit de miller
US4151485A (en) * 1977-11-21 1979-04-24 Rockwell International Corporation Digital clock recovery circuit

Also Published As

Publication number Publication date
NO148730C (no) 1983-11-30
FI67004B (fi) 1984-08-31
US4360926A (en) 1982-11-23
DK149380B (da) 1986-05-20
NO793303L (no) 1980-04-15
DK149380C (da) 1987-01-19
WO1980000904A1 (en) 1980-05-01
DK253180A (da) 1980-06-12
NO148730B (no) 1983-08-22
SE414104B (sv) 1980-07-07
FI792894A (fi) 1980-04-14
FI67004C (fi) 1984-12-10

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