GB1527732A - Digital phase locked loop - Google Patents

Digital phase locked loop

Info

Publication number
GB1527732A
GB1527732A GB1661175A GB1661175A GB1527732A GB 1527732 A GB1527732 A GB 1527732A GB 1661175 A GB1661175 A GB 1661175A GB 1661175 A GB1661175 A GB 1661175A GB 1527732 A GB1527732 A GB 1527732A
Authority
GB
United Kingdom
Prior art keywords
counter
output
input
register
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB1661175A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micro Consultants Ltd
Original Assignee
Micro Consultants Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micro Consultants Ltd filed Critical Micro Consultants Ltd
Priority to GB1661175A priority Critical patent/GB1527732A/en
Publication of GB1527732A publication Critical patent/GB1527732A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/181—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

1527732 APC systems; telegraphy-data transmission; synchronizing MICRO CONSULTANTS Ltd 15 July 1976 [22 April 1975] 16611/75 Headings H3A and H4P A digital phase locked loop suitable for extracting the clock signal from the transitions in an input data in the form of a biphase or delay modulation (Miller) coded signal and derived from tape recording, reproducing apparatus or long distance signalling arrangement comprises a controlled oscillator 10, a digital counter 13, a register 15 responsive to an input trigger from an input signal transition detector 14 to store the counter output and to supply the previously stored value via a D/A converter 11 to the oscillator 10. A variable divider 12 enables the loop to lock to wide range of input frequencies. A phase offset between the input signal and the output of counter 13 is avoided by feeding the register 15 output to an up/down counter 16 controlled by the input signal and using the output of 16 to control a further up/down counter 17. The outputs of the register 15 and the counter 17 are added at 19. The extracted clock may be utilized to convert in a decoder the received serial coded data to a non-return to zero format.
GB1661175A 1976-07-15 1976-07-15 Digital phase locked loop Expired GB1527732A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB1661175A GB1527732A (en) 1976-07-15 1976-07-15 Digital phase locked loop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB1661175A GB1527732A (en) 1976-07-15 1976-07-15 Digital phase locked loop

Publications (1)

Publication Number Publication Date
GB1527732A true GB1527732A (en) 1978-10-11

Family

ID=10080461

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1661175A Expired GB1527732A (en) 1976-07-15 1976-07-15 Digital phase locked loop

Country Status (1)

Country Link
GB (1) GB1527732A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0032253A1 (en) * 1980-01-08 1981-07-22 E-Systems Inc. Demodulator carrier recovery loop and method for demodulating a signal
FR2564664A1 (en) * 1984-05-15 1985-11-22 Adam Pierre Device for recovering a periodic signal
CN106603449A (en) * 2016-04-29 2017-04-26 福建先创电子有限公司 Clock synchronization FPGA structure and clock synchronization method based on GAD timing detection position

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0032253A1 (en) * 1980-01-08 1981-07-22 E-Systems Inc. Demodulator carrier recovery loop and method for demodulating a signal
FR2564664A1 (en) * 1984-05-15 1985-11-22 Adam Pierre Device for recovering a periodic signal
CN106603449A (en) * 2016-04-29 2017-04-26 福建先创电子有限公司 Clock synchronization FPGA structure and clock synchronization method based on GAD timing detection position

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee