SE7511637L

SE7511637L - DIFFERENT DATA TRANSFER SYSTEM

Info

Publication number: SE7511637L
Application number: SE7511637A
Authority: SE
Inventors: K Korver
Original assignee: Northern Electric Co
Priority date: 1974-10-16
Filing date: 1975-10-16
Publication date: 1976-04-20
Also published as: CA996691A; NL180799C; FR2331222A1; SE402510B; IT1043321B; FR2331222B1; GB1522682A; DE2546422C2; JPS5172201A; NL180799B; NL7511655A; DE2546422A1

Abstract

1522682 Duplex data transmission NORTHERN TELECOM Ltd 3 Oct 1975 [16 Oct 1974] 40614/75 Headings H4P and H4M In a full duplex transmission system, more particularly for the control channel of a 4-wire telephone system, data from the local station has two transitions for bits of one level and four transitions for the other level. At the remote station two sync pulse trains are produced, one for each transition rate and these are used to decode the signal. Signals are returned to the local station at the lower transition rate, the delay in the transmission being less than half the period of the lower rate. A data "1" at 5 is gated by half rate clock pulses through NAND gate 20 and flip-flop 21 in synchronism with the full rate clock. When the data is "0" full rate pulses are gated through the Exclusive OR gate 23. The resulting signals (Fig. 2F not shown) pass through a hybrid and filter circuit 24 to line as diphase signals. On reception incoming signals are squared and provided with DC bias by 32, energizing, via steering circuit 33, a non-retriggerable monostable circuit 34 having an upset time of between half and one period of clock rate. Regenerated signal from 34 is applied, via inverting amplifier 35, to CL input of flip-flop 36 together with an input from 32 producing a partly decoded signal; OR gate 37 and flip-flop 38 provide half rate signals in phase with lower rate portion of di-phase signals. Flip-flop 38 also receives an output from 34 to provide half rate clock signals (Fig. 2J) which are applied to a flip-flop 39 to complete decoding process, output being passed to supervisory circuit 13 of unspecified purpose. Flip-flop 38 is reset by OR'ed inputs from flip-flop 36 in the event that output is out of phase with slower rate portion of di-phase signal. Supervisory circuit 13 also generates binary data applied through flip-flop 40 OR 41 both receiving half rate clock pulses from 38, and hybrid circuits 30, 24 to shape V 52 which squares, also restores DC bias on reception before decoding at 53 by half rate clock pulses.