FR2335102A1 - Differential biphase binary code decoder - measures time intervals between pulses over preset period to increase maximum data transmission rate - Google Patents

Differential biphase binary code decoder - measures time intervals between pulses over preset period to increase maximum data transmission rate

Info

Publication number
FR2335102A1
FR2335102A1 FR7531694A FR7531694A FR2335102A1 FR 2335102 A1 FR2335102 A1 FR 2335102A1 FR 7531694 A FR7531694 A FR 7531694A FR 7531694 A FR7531694 A FR 7531694A FR 2335102 A1 FR2335102 A1 FR 2335102A1
Authority
FR
France
Prior art keywords
data transmission
transmission rate
time intervals
binary code
preset period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7531694A
Other languages
French (fr)
Other versions
FR2335102B1 (en
Inventor
Jean-Pierre Houdard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel CIT SA
Original Assignee
Alcatel CIT SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel CIT SA filed Critical Alcatel CIT SA
Priority to FR7531694A priority Critical patent/FR2335102A1/en
Publication of FR2335102A1 publication Critical patent/FR2335102A1/en
Application granted granted Critical
Publication of FR2335102B1 publication Critical patent/FR2335102B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)

Abstract

Decoding system for signal trains in a differential biphase binary code where it is normally necessary to know the frequency and phase of the clock source signals synchronising the incoming message. The system overcomes the response time problems associated with using a local clock and synchronisation words in the message and to increase the data transmission rate. The decoder uses measurement of time intervals between selected pulses over some preset period, and delivers a local clock pulse in response to each such pulse. A further circuit detects the presence or otherwise of a transition pulse between them, both circuits being based on local clock source synchronised comparators.
FR7531694A 1975-10-16 1975-10-16 Differential biphase binary code decoder - measures time intervals between pulses over preset period to increase maximum data transmission rate Granted FR2335102A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7531694A FR2335102A1 (en) 1975-10-16 1975-10-16 Differential biphase binary code decoder - measures time intervals between pulses over preset period to increase maximum data transmission rate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7531694A FR2335102A1 (en) 1975-10-16 1975-10-16 Differential biphase binary code decoder - measures time intervals between pulses over preset period to increase maximum data transmission rate

Publications (2)

Publication Number Publication Date
FR2335102A1 true FR2335102A1 (en) 1977-07-08
FR2335102B1 FR2335102B1 (en) 1978-05-12

Family

ID=9161272

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7531694A Granted FR2335102A1 (en) 1975-10-16 1975-10-16 Differential biphase binary code decoder - measures time intervals between pulses over preset period to increase maximum data transmission rate

Country Status (1)

Country Link
FR (1) FR2335102A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2542532A1 (en) * 1983-03-11 1984-09-14 Cit Alcatel Circuit for recovering the timing of a synchronous data transmission using a combination of the L two-phase and modified two-phase codes
FR2542535A1 (en) * 1983-03-11 1984-09-14 Cit Alcatel Method of synchronous data transmission and system for its implementation
EP0121750A1 (en) * 1983-03-11 1984-10-17 Alcatel Clock recovery circuit for a synchronous data transmission utilizing a combination of the biphase L code, and the modified biphase code

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN" VOLUME 17, NO.7, DECEMBRE 1974. ARTICLE DE DWIRE: "FIXED TIME BASE F2F DATA CLOCK SEPARATOR CIRCUIT" PAGES 2109-2110.) *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2542532A1 (en) * 1983-03-11 1984-09-14 Cit Alcatel Circuit for recovering the timing of a synchronous data transmission using a combination of the L two-phase and modified two-phase codes
FR2542535A1 (en) * 1983-03-11 1984-09-14 Cit Alcatel Method of synchronous data transmission and system for its implementation
EP0121750A1 (en) * 1983-03-11 1984-10-17 Alcatel Clock recovery circuit for a synchronous data transmission utilizing a combination of the biphase L code, and the modified biphase code

Also Published As

Publication number Publication date
FR2335102B1 (en) 1978-05-12

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Legal Events

Date Code Title Description
ST Notification of lapse