GB1522682A - Two wire full duplex data transmission system - Google Patents
Two wire full duplex data transmission systemInfo
- Publication number
- GB1522682A GB1522682A GB4061475A GB4061475A GB1522682A GB 1522682 A GB1522682 A GB 1522682A GB 4061475 A GB4061475 A GB 4061475A GB 4061475 A GB4061475 A GB 4061475A GB 1522682 A GB1522682 A GB 1522682A
- Authority
- GB
- United Kingdom
- Prior art keywords
- flop
- flip
- rate
- signals
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M9/00—Arrangements for interconnection not involving centralised switching
- H04M9/002—Arrangements for interconnection not involving centralised switching with subscriber controlled access to a line, i.e. key telephone systems
- H04M9/003—Transmission of control signals from or to the key telephone set; signalling equipment at key telephone set, e.g. keyboard or display equipment
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Bidirectional Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Dc Digital Transmission (AREA)
- Sub-Exchange Stations And Push- Button Telephones (AREA)
Abstract
1522682 Duplex data transmission NORTHERN TELECOM Ltd 3 Oct 1975 [16 Oct 1974] 40614/75 Headings H4P and H4M In a full duplex transmission system, more particularly for the control channel of a 4-wire telephone system, data from the local station has two transitions for bits of one level and four transitions for the other level. At the remote station two sync pulse trains are produced, one for each transition rate and these are used to decode the signal. Signals are returned to the local station at the lower transition rate, the delay in the transmission being less than half the period of the lower rate. A data "1" at 5 is gated by half rate clock pulses through NAND gate 20 and flip-flop 21 in synchronism with the full rate clock. When the data is "0" full rate pulses are gated through the Exclusive OR gate 23. The resulting signals (Fig. 2F not shown) pass through a hybrid and filter circuit 24 to line as diphase signals. On reception incoming signals are squared and provided with DC bias by 32, energizing, via steering circuit 33, a non-retriggerable monostable circuit 34 having an upset time of between half and one period of clock rate. Regenerated signal from 34 is applied, via inverting amplifier 35, to CL input of flip-flop 36 together with an input from 32 producing a partly decoded signal; OR gate 37 and flip-flop 38 provide half rate signals in phase with lower rate portion of di-phase signals. Flip-flop 38 also receives an output from 34 to provide half rate clock signals (Fig. 2J) which are applied to a flip-flop 39 to complete decoding process, output being passed to supervisory circuit 13 of unspecified purpose. Flip-flop 38 is reset by OR'ed inputs from flip-flop 36 in the event that output is out of phase with slower rate portion of di-phase signal. Supervisory circuit 13 also generates binary data applied through flip-flop 40 OR 41 both receiving half rate clock pulses from 38, and hybrid circuits 30, 24 to shape V 52 which squares, also restores DC bias on reception before decoding at 53 by half rate clock pulses.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA211,515A CA996691A (en) | 1974-10-16 | 1974-10-16 | Tow wire, full duplex data transmission system |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1522682A true GB1522682A (en) | 1978-08-23 |
Family
ID=4101371
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB4061475A Expired GB1522682A (en) | 1974-10-16 | 1975-10-03 | Two wire full duplex data transmission system |
Country Status (8)
Country | Link |
---|---|
JP (1) | JPS5172201A (en) |
CA (1) | CA996691A (en) |
DE (1) | DE2546422C2 (en) |
FR (1) | FR2331222A1 (en) |
GB (1) | GB1522682A (en) |
IT (1) | IT1043321B (en) |
NL (1) | NL180799C (en) |
SE (1) | SE402510B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0040632A1 (en) * | 1979-11-26 | 1981-12-02 | Ncr Co | Data processing system with serial data transmission between subsystems. |
EP0174124A2 (en) * | 1984-08-24 | 1986-03-12 | Unisys Corporation | Fiber optic workstation datalink interface |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5474602A (en) * | 1977-11-28 | 1979-06-14 | Hitachi Ltd | Photo delivery unit of synchronous type |
JPS5814104B2 (en) * | 1978-04-28 | 1983-03-17 | 株式会社東芝 | Information transmission method |
EP0059493B1 (en) * | 1981-02-27 | 1985-01-23 | BBC Aktiengesellschaft Brown, Boveri & Cie. | Arrangement for decoding a biphase coded signal, as well as utilisation of the arrangement |
JPS58151154A (en) * | 1982-03-03 | 1983-09-08 | Hitachi Ltd | Transmission system between devices |
CN115314071A (en) * | 2022-08-12 | 2022-11-08 | 程艳 | Full-duplex bidirectional analog front-end hybrid transceiver |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1216759A (en) * | 1968-05-23 | 1970-12-23 | Standard Telephones Cables Ltd | Subscriber subset for p.c.m. telephone system |
GB1182363A (en) * | 1968-07-26 | 1970-02-25 | Standard Telephones Cables Ltd | Subscriber Subset for PCM Telephone System |
GB1229149A (en) * | 1969-07-28 | 1971-04-21 | ||
US3637939A (en) * | 1970-05-07 | 1972-01-25 | Bell Telephone Labor Inc | Line status control for electronic key telephone system |
-
1974
- 1974-10-16 CA CA211,515A patent/CA996691A/en not_active Expired
-
1975
- 1975-10-03 NL NL7511655A patent/NL180799C/en not_active IP Right Cessation
- 1975-10-03 GB GB4061475A patent/GB1522682A/en not_active Expired
- 1975-10-13 IT IT2822575A patent/IT1043321B/en active
- 1975-10-15 JP JP12334975A patent/JPS5172201A/en active Pending
- 1975-10-15 FR FR7531587A patent/FR2331222A1/en active Granted
- 1975-10-16 DE DE19752546422 patent/DE2546422C2/en not_active Expired
- 1975-10-16 SE SE7511637A patent/SE402510B/en not_active IP Right Cessation
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0040632A1 (en) * | 1979-11-26 | 1981-12-02 | Ncr Co | Data processing system with serial data transmission between subsystems. |
EP0040632A4 (en) * | 1979-11-26 | 1982-04-29 | Ncr Corp | Data processing system with serial data transmission between subsystems. |
EP0174124A2 (en) * | 1984-08-24 | 1986-03-12 | Unisys Corporation | Fiber optic workstation datalink interface |
EP0174124A3 (en) * | 1984-08-24 | 1988-09-07 | Unisys Corporation | Fiber optic workstation datalink interface |
Also Published As
Publication number | Publication date |
---|---|
FR2331222A1 (en) | 1977-06-03 |
JPS5172201A (en) | 1976-06-22 |
NL7511655A (en) | 1976-04-21 |
DE2546422C2 (en) | 1986-12-18 |
FR2331222B1 (en) | 1981-10-09 |
SE7511637L (en) | 1976-04-20 |
DE2546422A1 (en) | 1976-04-22 |
NL180799B (en) | 1986-11-17 |
CA996691A (en) | 1976-09-07 |
IT1043321B (en) | 1980-02-20 |
SE402510B (en) | 1978-07-03 |
NL180799C (en) | 1987-04-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4267595A (en) | AMI Decoder apparatus | |
US3967061A (en) | Method and apparatus for recovering data and clock information in a self-clocking data stream | |
EP0040632B1 (en) | Data processing system with serial data transmission between subsystems | |
WO1985002959A1 (en) | A digital communications system | |
GB1356878A (en) | Data communication system | |
US3953673A (en) | Digital data signalling systems and apparatus therefor | |
US4325053A (en) | Method and a circuit for decoding a C.M.I. encoded binary signal | |
GB1522682A (en) | Two wire full duplex data transmission system | |
DE3065620D1 (en) | Method and device for coding digital data, device for decoding digital data and a transmission system comprising such a device | |
US5101401A (en) | Polarity judging arrangement by using frame synchronization signals of a received signal | |
GB1402176A (en) | Computer interface coding and decoding apparatus | |
GB1167599A (en) | Biphase Signals Sequence Identification System | |
GB1489286A (en) | Digital data transmission | |
GB1154711A (en) | Digital Communications Systems | |
GB1382324A (en) | Digital voice interpolation system for pcm systems | |
EP0066620B1 (en) | Circuit for clock recovery | |
US3394312A (en) | System for converting two-level signal to three-bit-coded digital signal | |
GB1321695A (en) | Data communication system for servicing two different types of remote terminal units over a single transmission line | |
JPS6242544B2 (en) | ||
US4230903A (en) | Data transmission system | |
US3939307A (en) | Arrangement for utilizing all pulses in a narrow band channel of a time-division multiplex, pulse code modulation system | |
US3610832A (en) | Apparatus for adapting pcm telephone systems to multiplexed telegraph use | |
US3524938A (en) | Output circuit for pulse code modulation time sharing system | |
GB1470547A (en) | System for transition-coding binary information | |
GB1066909A (en) | Improvements in or relating to electrical signalling systems |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |