JPS58151154A - Transmission system between devices - Google Patents

Abstract

PURPOSE:To obtain a digital signal transmission circuit excellent in SN ratio, by probiding a PM encoding circuit for a transmission section for balanced transmission in suppressing DC components, and monitoring the relation of complementary of PM codes at a signal reproducing and monitoring circuit of a reception section. CONSTITUTION:Transformers 31, 32 are provided at the post-position of a cable driver element 10 of the transmission section and at the pre-position of a cable receiver element 20 of a reception section to two devices 1, 2 having different grounding systems to separate ground potentials EA, EB and the reduction in noise margin of each element is prevented. Further, an exclusive logical sum element 11, a clock pulse forming section 12 and a flip-flop 13 are provided at the pre-stage of the element 10 to provide complementary logical values by using a clock pulse of duty cycle 50%. Thus, a digital signal is converted into the PM (phase modulation) code consisting of two-bit of ''01'' or ''10'', and the DC components are suppressed, allowing to perform balanced transmission via the transformers 31, 32 and the cable 3.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a digital signal transmission system between two devices with different grounding systems.

Conventionally, two devices were connected with a cable to create a digital l! When transmitting 't, a balanced transmission method is used as a method with excellent noise resistance.

Structure of balanced transmission system
Cable driver element 10° of the transmitting part of 11ilI, terminating resistor 22 of the receiving part of the device (#) 21M, cable receiver element 20, and balanced transmission cable 5 connecting these
In some cases, JK common mode
A checkerboard 21 is provided to remove in-phase components of noise mixed into the cable.

In such a configuration, there are cases where it is desired to provide a separate grounding system for each device from the noise countermeasure section. At this time, if the ground potentials EA and El of one device fluctuate, a potential difference will be created between the grounds of both devices, and bias will be applied to the driver output and receiver input sections at both ends of the cable, reducing the margin for noise, which will easily lead to noise operation. This causes the problem of becoming.

One solution to this drawback is to isolate both devices galvanically, and existing implementation methods include using photocubs 2 and transformers. Of these, the former has the disadvantage that it is not possible to obtain a single unit that maintains high reliability over a long period of time, while the latter requires the selection of a signal format that suppresses the DC component of the signal! At the same time, countermeasures against vibration caused by ground noise etc. are desired.

An object of the present invention is to solve the above-mentioned drawbacks and to realize digital signal transmission with excellent resistance to noise with a simple circuit configuration.

The main point of the present invention is to use a transformer to separate the earth system,
A KPM encoding circuit is provided in the transmitting section to realize balanced transmission with DC components suppressed, and a signal regeneration monitoring circuit in the receiving section monitors the complement relationship of the PM code, and when an error is detected, the decoded digital signal is converted into a safe one. There is a need to convert it to a logical value.

Below is the book! ! The details of the transmission method according to the present invention will be explained below.

#I2 is a diagram showing an example of the configuration of digital transmission in the present invention.

ji! In Figure 2, there are two devices with different grounding systems (A
) 1 # (B) In contrast to 2, a transformer 51. ! i2 is provided to separate the ground potentials EA and Ej to prevent the noise margin of each element from decreasing. Further, in front of the cable driver element 1o, an exclusive logic circuit 11, a clock pulse generator 12, and an arrival flop 13 are provided, and the clock pulse of the device 50 is used to generate a signal as shown in FIG. Adds complementary logical value to . From this K, the digital signal is converted into a PM (phase change M) code consisting of 2 bits "ol" or "1o", and the DC component is suppressed, so balanced transmission via transformers 31 and 52 and cable S is possible. becomes. In addition, in the transmitter, 14
indicates the resistance for electric *l111 only. In the receiving section, the digital signal can be reproduced more easily than by extracting only one of the two bits.

In the receiving section, an error protection circuit 25 is installed. After the above code is received by the cable receiver element 2o via the transformer 52 and the terminating resistor 22, two 7-rep-frog 25.24K 2-phase clock pulses are generated! Set each bit. The timing relationship at this time is shown in jI4 fat. In Figure 4, the l-phase lock pulse sets the first bit to 7.
Set it to RipFlotz 123, and ■ Reciprocal lock pulse is the complement JI! 2 bits to another flip-flop 24
Set to . The circuit 25 following these flip 70 tubes 25 and 24 monitors that the two values are complementary to each other, and when normal, jl! 1 of 7 lip flop 25
The value of is transmitted to the subsequent stage as a received digital signal. on the other hand,
If the transmission signal is temporarily disturbed due to noise contamination, etc., the above-mentioned complement relation will no longer hold, and the outputs of the two 7 lip-flops 23 and 24 will be "0" and "0", or "1".
becomes "1". When the error protection circuit 25 detects this combination, it outputs a fixed logical value instead of the received signal. As this fixed value, a value that makes the system including devices A and B fail safe is selected and set at the time of circuit configuration.

As explained above, according to the present invention, 'Is! A configuration with excellent durability is realized, and the circuit can be easily configured with 4 to 5 integrated circuits and transformers per signal line.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram showing an example of the configuration of conventional balanced transmission, Figure 2 is a schematic diagram showing an example of the configuration of the inter-device transmission system according to the book, and Figure 5 is a timing diagram showing complement addition in transmission sK. Figure 4 shows the timing of signal extraction at Uke 4Mm. 1: Device A 2: Device B 3: Balanced transmission cable 10: Cable driver element 11: #axial OR element 12: Clock pulse generation giit+ 15.231, 24: Flip-flop 14: Current limiting resistor 20: Couple Receiver element 22: Resistance to terminal #25: Resistance circuit 51.5
2:) Reims's patent attorney Usuki EB $J Umbrella. 3 years old 41EI Continued from page 1 0 Inventor: Kozo Murakami Fujitsu Limited, 1015 Kamiodanaka, Nakahara-ku, Kawasaki City ■Applicant: Nippon Telegraph and Telephone Public Corporation ■Applicant: Oki Electric Industry Co., Ltd. Toranomon, Minato-ku, Tokyo 1-7-12 ■Applicant Nippon Densaku Co., Ltd. 5-33-1 Shiba, Minato-ku, Tokyo ■Applicant Fujitsu Ltd. 1015 Kamiodanaka, Nakahara-ku, Kawasaki City

Claims (1)

[Claims] In digital signal transmission between two devices with different grounding systems, the transmitting section and receiving section of both devices are connected with a balanced transmission cable, the transmitting section is provided with a KPM encoding circuit and a cable driver element for balanced transmission, and the receiving section is provided with a KPM encoding circuit and a cable driver element for balanced transmission. A cable receiver element for balanced transmission and a signal regeneration monitoring circuit are provided in the cable, and a transformer is provided in one or both of the transmitting section and the receiving section. An inter-device transmission system comprising means for decoding a code into an original digital signal, means for monitoring the normality of a PM code, and means for determining a logical value of an output digital signal when a PM code is abnormal.