SE524477C2 - Arrangement for an electric converter - Google Patents

Abstract

A converter, adapted to be connected to a three-phase input voltage system (V1, V2, V3), comprising a first terminal (P) and a second terminal (N) of a DC voltage output is presented. It comprises for each phase of the input voltage system, two boost diodes (DB1, DB2, DB3, DB4, DB5, DB6), a switch (S1, S2, S3) and a snubber circuit (1, 2, 3). For each phase, a snubber inductor (L11, L12, L13) in series with each switch (1,2,3) reduces the current rising rate at the turn-on instant. When the switch (1,2,3) is turned-off a capacitor (C12, C13, C22, C23, C32, C33) delays the voltage rising by diverting the current that is circulating through the switch. The invention presents a very efficient converter having only one inductor per snubber circuit, which saves both space and cost.

Description

'20 524 477 = a:. | . «. ~ n c a. . ø «| The current article does not allow control of output voltage, and the harmonic distortion can increase if the articulation angle of the switches is chosen to deviate more than 30 degrees.

Therefore, the applications with this type of control are limited.

To improve the waveform of the line current and the controllability of the three-phase converter, pulse width modulation (PWM) is usually used. The input current is controlled by varying the pulse width of the switch units, which usually operate at a high frequency.

In order to reduce the loss energy in the switch unit during the commutation event, a so-called "Snubber" circuit ("transient limiter circuitÜ"), which limits the current and voltage rise velocity at the respective switch-on time and switch-off time. An advantage of "snubber circuits" is that they can reduce the EMI (electromagnetic interference) caused by the svifitch function in the converter.

Constant frequency resonant transducers combine tuning methods for low loss switching with PWM for control.

Passive “snubbers” are preferable to active “snubbers”, as no additional active components are needed, thereby reducing cost and complexity, and increasing robustness and reliability.

Fig. 1 shows a circuit on a passive snubber for a three-level AC-DC converter, which circuit was introduced in [C, Cruz and I. Barbi "A passive lossless snubber for the high power factor unidirectional three-phase three-level rectifiers", Proceedings of IE- CON'99, Vol.2, p. 909-914, 1999]. The dubber limits the growth value of the conduction current and the switching voltage only with passive components. The converter has a high efficiency and the snubber is mainly lossless. However, the dude requires a relatively large number of passive components. This not only contributes to a high manufacturing cost, but also to a large area on the printed circuit board, which in turn contributes to a large system size and relatively low power density. The energy due to the switch-on and switch-off process is first stored in an inductive and a capacitive element, respectively, and is then fed to the load and contributes to the so-called lossless commutation.

SUMMARY One purpose of the invention is to present a unidirectional three-level converter, which has the same advantages as previously known converters and which has a higher power density.

Another object of the invention is to present a unidirectional three-level converter with high power density and low electromagnetic interference.

These objects are realized with a converter, of an initial type, which has the characterizing features of claim 1.

The snub inductor in series with each switch element reduces, during operation, the rise time of the current at the switch on, so that the switch-on transition takes place initially at zero and then with a slowly rising current. It is connected between the connection with two saving diodes and a bidirectional switch, and prevents the harmful effect that the saving current of the saving diode has on the switches.

According to the invention, only one inductor is used to prevent the reverse recovery current of both saving diodes in each phase. Thus, the same inductor is used in both the positive and negative half periods of the input voltage, and the invention allows saving of a resonant inductor per phase. Therefore, compared to the current state of the art, the circuit, in accordance with the present invention, allows the saving of three resonant inductors.

The resonant inductors are among the most volume-intensive components and are obviously also among the most expensive components in the circuit. Therefore, f20 =; 524 477 1 a. - a a: n s | ø «| 1 n 4 a o wo 4 reduction of the number of resonant inductors to reduce the cost and the complete system volume and improve the power density.

Elements for limiting the rise time of the voltage preferably comprise a second and a third snubber capacitance. When the switch unit is turned off, these capacitances will delay the voltage increase by diverting the current circulating through the switch.

This “lossless attenuation” functions as energy storage in passive elements (inductors and capacitances) due to the switching process, to then transfer the energy to a load.

It is important to note that the invention retains the favorable characteristic three-level boost-type hois converters (voltage multipliers) type such as: low voltage pressure on the switch elements, high quality waveforms, no shot-through and generation. of the two symmetrical output voltages The converter according to the invention operates with soft switching without the use of additional switches.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will now be described in more detail with reference to the drawings in which: fi g. Fig. 1 shows a three-phase three-level converter with a passive snubber according to prior art, Fig. 2 shows a simplified circuit diagram for a three-phase three-level "boost" converter with a passive "snubber" according to a preferred embodiment of the invention, Figs. 3a-3f show alternative details in the converter in Fig. 2, Figs. 4 show voltage and current diagrams in the circuit in Fig. 2, Fig. 5 shows the design of a circuit coit for a converter according to the prior art, Fig. 6 shows the design of a circuit board for a converter. according to the invention, '20 524 477 a »oo: n fi g.7 shows a simplified circuit diagram for a three-phase three-level boost converter with a passive" snubber "according to an alternative embodiment of the invention, and fi g.8 shows a simplified circuit diagram for a three-phase three-level "Boostï converter with a passive" snubber "according to another embodiment of the invention.

DETAILED DESCRIPTION Fig. 2 shows a circuit diagram of a three-level converter according to a preferred embodiment of the invention. The converter is connected to a three-phase voltage system V1, V2, V3 through three additional inductors L1, L2, L3. One of two connection terminals in each auxiliary inductor is connected to separate points A, B, C. Each inductor's second connection terminal is connected to a point U, V resp. W.

The converter includes first DB1, DB3, DB5 and second DB2, DB4, DB6 save diodes. The anodes of the first savings diodes DB1, DB3, DB5 and the cathodes of the second savings diodes DB2, DB4, DB6 are connected to points U, V and W. The cathodes of the first saving diodes DB1, DB3, DB5 are connected to a point P, which represents the positive tenninal of a DC output. In the same way, the anodes on the other saving diodes DB2, DB4, DB6 are connected to a point N, which represents the negative terminal of the voltage output. The points P and N are intended to have a load LD connected between them.

Two capacitors are connected to the output terminals. A first capacitance C1 is connected between the positive terminal P and a center point M, which is a reference for the positive and negative output voltages at the points P and N. A second capacitance C2 is connected between the center point M and the negative terminal N.

Three bidirectional switches S1, S2 and S3 are connected to the center point M at one end and to the points R, S and T at the other end. The bidirectional switches are represented as ideal switches in Fig. 2. In practice, they may have any of the configurations shown in Figs. 3a-3f.

Three passive snubber circuits 1, 2, 3 are connected between the spare diodes and the bidirectional switches, (In Fig. 2, each snubber circuit 1, 2, 3 is shown as enclosed in a rectangle of dashed lines.) The snubber circuits have similar configuration, and were and one comprises a first C11, C21, C31, a second C12, C22, C32, a third C13, C23, C33 and a fourth C14, C24, C34 snubber capacitance, as well as a first D11, D21, D31, a second D12, D22, D32, a third D13, D23, D33, a fourth D14, D24, D34, a fifth D15, D25, D35 and sixth D16, D26, D36 snubber diode. Preferably, the snubber cliodes should be of the ultra-fast type. In addition, each snubber circuit 1, 2, 3 contains a snubber inductor L11, L12, L13.

The snub circuit 1 is connected to the rectifier as follows. The snubber inductor L11 is, at a first connection terminal 4 on the snubber inductor, connected to a point U, which is an interconnection of the first and the second of the saving diodes DB1, DB2, and, at a second connection terminal 5 of the snubber inductor, connected to the bi-directional switch S1 via a point R.

The snubber inductor L11 thereby reduces the slope value of the current through the Slvid switch at the moment of switch-off. This avoids the dangerous effect that the recovery current of the saving diodes has on the switches. According to the invention, for each phase only one inductor is used to prevent the return current of both diodes.

The third and fourth snubber diodes D13, D14 connect the snubber inductor L11 to the second and the third snubber capacitance C12, respectively. C13 through the switch S1 at a switch-on moment for the switch. The anode of the third snubber diode D13 is connected to the point R and its cathode to a point F1. The cathode of the fourth snubber diode D14 is connected to the point R and its anode to a point G1. «20 524 477 e .. .- 7 The second and third capacitances C12, C13 are used to limit the rise of the voltage in the switch S1 at the switch-off torque. They are, at one end, connected to point M. The other end of the second snubber capacitance C12 is connected to point F1 and the other end of the third snubber capacitance C13 is connected to point G1.

The second snubber diode D12 forms a path for energy transfer depending on the commutations from the snubber inductor L11 and the second snubber capacitance C12 to the first snubber capacitance C11. Similarly, the snubber diode D15 forms a path for transmitting the energy due to the commutations from the snubber inductor L11 and the third snubber capacitance C13 to the fourth snubber capacitance C14. This energy is transferred to the load LD to prevent cover losses. The anode of the second snubber diode D12 is connected to the point F1 and its cathode to a point E1. The anode of the fifth snubber diode D15 is connected to a point H1, and its cathode is connected to the point G1.

The first and fourth snubber capacitors C11, C14 temporarily store the switching energy, which is then transmitted to the load LD via the first and sixth snubber diodes D11 and D16, respectively. The first and fourth snubber capacitances C11 and C14 are interconnected at one end to point U and at the other end to points E1 and H1, respectively.

Finally, the diodes D11 and D16 form the necessary path to transfer the stored energy in C11 and C14 to the load LD. The anode of the first snubber diode D11 is connected to the point E1 and its cathode to the positive output terminal P. The cathode of the sixth snubber diode D16 is connected to the point H1 and its anode to the negative output terminal N.

The snubber circuits 2 and 3 are connected to the rectifier in the same way as the snubber circuit 1 described above. Fig. 4 shows now, as a function of time, the currents through the snubber inductor L11, i (L1 l), and the switch S1, i (S1), and the voltage across the switch S1, v (S1), the the second snubber capacitance C12, v (C12), and the first snubber capacitance C11, v (C1 1).

To make this easier to understand, it is assumed that the current flowing through the addition inductance L1, here referred to as input current, is constant with a value I, during the switching period. Similarly, the voltage across the first output capacitance C1, referred to herein as the output voltage, is kept constant at a value V01.

In the beginning, before t0, the switch S1 is in the off position, and the input current fl flows through the auxiliary inductor L1 and the first saving diode DB1 to the first output capacitance C1 and the load LD. The current through the snubber inductor L11, i (L11), and the switch S1, i (S1), is equal to zero, while the voltage across the second snubber capacitance C12, v (Cl2), and the switch S1, v (S1), is equal to Vol, and the voltage across the first snubber capacitance C1, v (C1 1) is equal to zero.

At time t0, the switch S1 goes into mode, and since the first saving diode DB1 also conducts, the output voltage Vol is applied across the connection terminals 4, 5 of the snubber inductor L11. Consequently, the current through the snubber inductor L11, i (L1 l), and the switch S1, i (S1), will increase by an amount according to: fi l fi dr L11 The current circulating through the first saving diode DB1 will decrease by the same amount. When this current has dropped to zero, it will change direction and continue to circulate through the first saving diode DB1 for a short time determined by the conduction characteristics of the diode. Then, at time t1, the first saving diode DB1 will switch to the latch state. Up to this time, the voltages across the first snubber capacitance C1, v (C1), and the second snubber capacitance C12, v (C12) will remain zero and Vol, respectively.

When the first saving diode DB1 goes into a voltage state at time t1, the second snubber diode D12 will start conducting the current through a loop formed by the 524 477 u. . u. «~ Ø, - - | u w .- 9 the second snubber diode D 12, the first snubber capacitance C1, the snubber inductor L11, the switch S1 and the second snubber capacitance C12. Through a time interval from t1 to t2, the energy stored in the second snubber capacitance C12 is transferred to the first snubber capacitance C1. The voltage across the second snubber capacitance C12 decreases from V01 to zero, while the current through the snubber inductor L11 and the switch S1 continues to increase. The tuned transmission from t1 to t2 is determined by the equation of the current through the snubber inductor L11, i (L11), which is given by: V01 f1,. (F) = 1 + wßLn-sinßfß-t) and the voltage across the second snubber capacitance C12 , v (C12) is given by: 2 2 vm (t) = V0 1- (022 - [cos (wt) + w 2 4:! w m2 The voltage across the first snubber capacitance C1 1, v (C1) is given by: m1: Vc | i (t) = V01 ° í {"11" 'C0s (wt) 1 where - 2 1 1 C_ C11 C1 1, ___-__, 1 = --_, and w2 = _-_-.

JLn-c C11 + c12 ww / Lii-Cii i / Lii-ciz w: Once the second snubber capacitance C12 is completely discharged at time t2, the third snubber diode D13 switches to conductive state, and the inductor current starts circulating in a loop formed by diodes D13 and D12, the first snubber capacitance C11 and the snubber inductor L11. The current through switch S1 is not: A52 is no longer equal to the current through the snubber inductor L11. While the switch S1 conducts the input current I to the load LD, the snubber inductor L11 conducts the input current I plus the current circulating through the loop formed by D13, D12, the first snubber capacitance C11 and the snubber inductor L11. During a time interval from t2 to t3, the energy stored in the snubber inductor L11 is transferred to the first snubber capacitance C11. During this stage, the current through the snubber inductor L11 decreases until it becomes equal to the input current I at time t3. During the resonance stage from t2 to t3, the current through the snubber inductor L11, i (L1 1) is given by _ V -x / Z- 22 --- 2 V -1. zL ,, (t) = I - + - -cos (wlt) --- -s1n (w1t) and the voltage across the first snubber capacitance C11, v (Cl1) is given by - sin (co1 -t) u 2 s 01 * a 2: 2 VCn (t) - .cos (ml.t) + Û) _ 22 Once the current through the snubber inductor L11 is equal to the input current at t3, the currents and voltages remain in the resonant elements (the snubber inductor L11, the first snubber capacitance C11 and the second snubber capacitance C12) and switch S1 constant. This step ends at t4 when the switch S1 is switched to the voltage state. Preferably, the switch is controlled by a gate command signal.

At time t4, the input current circulating through the switch S1 is driven over to the second snubber capacitance C12 via the third snubber diode D13. The voltage across the second snubber capacitance C12, v (C12), which was zero at t4, rises linearly by an amount given by Q_J__ dr C12: 524 477 ll u «. | n> e -. | a »This step ends at t5, when the sum of the voltage across the first snubber capacitance C11 plus the voltage across the second snubber capacitance C12 becomes equal to the output voltage Vol. The current through the snubber inductor L1 1 and the voltage across the first snubber capacitance C1 1 remain constant during this range from t4 to t5.

At time t5, the first snubber diode D1 becomes directly polarized and begins to conduct a portion of the input current toward the output. The remainder of the input current remains circulating through the second snubber capacitor C12, which continues to charge until the voltage between its terminals becomes equal to Vol. During the resonant state during the time interval from t5 to t6, the current through the snubber inductor is L11 íL11 (t) = I-: IC / 'Ill-šll-Cosçlrtïl and the voltage across the first snubber capacitance C11 is I-C. I-C 1 vc11 (t): ____'__ Sm (w'z) ííJlJ / oi -Voi arcuar -aren wz and the voltage across the second snubber capacitance C12 is I -C. I (01 "c-2 (fl = æffz's * nlw" 'ltaïziï "' t V01 'Vw 2,3 When the voltage across the second snubber capacitance C12 is equal to Vol at time t6, the snubber diode D12 will be directly polarized and begin to conducting a portion of the input current to the load LD via the first snubber diode D11, the remainder of the input current continues to circulate through the first snubber capacitance C11 and the first snubber diode D11.The current through the snubber inductor L11 continues f 524 477 u «Q« |. -. Since the time interval between t5 and t6 is very small, in order to meet the current equations for this resonant state, it is assumed that the values of the current and the voltage at t6 are the same as the values at t5 With this simplification, the current equations in the time interval from t6 to t7 are as follows: For the current through the snubber inductor L11: IL1i (t) = 1 V01 - Lnwz -sin (w1-z) For the voltage across the first snubber capacitance C11: 1 va] (t) = Vol - ï - cos (cul - t) m2 The voltage across the second snubber capacitance C12 remains unchanged equal to Vol.

At time, the current through the snubber inductor L1 1 becomes zero and remains at this value. During the time interval from t7 to t8, the input current circulates through the first snubber capacitance C11 and the first snubber diode D11 to the load LD.

The voltage across the first snubber capacitance C11 is reduced at a constant speed until it reaches the value zero. The equation which determines the voltage across the first snubber capacitance C11 is: (ul I vC ,, (z) = zš -, / VO, 2 _12 -L112 -wzz -a-ï-f At time t8 the voltage across the first snubber capacitance C11 becomes zero , and the first saving diode DB1 is directly polarized and conducts the input current towards the output, after which the currents and voltages across the snubber elements remain constant until a new cycle is initiated.

The conditions described above are valid for the positive half-period of the input voltage (phase A) and current commutation from the first saving diode DB] to the switch S1 and vice versa. During the negative half period, the current commutation takes place from the second saving diode DB2 to the switch S1 with the same corresponding state.

For the negative half period, the elements involved in soft commutation are the tripping inductor L11, the third tripping capacitance C13, the fourth tripping capacitance C14, the fourth D14, the fifth D15 and the sixth D16 tripping diode. It is important to note that the snubber inductor L11 was used in the positive and in the negative half period. The proposed invention thus allows saving of a resonant inductor per phase.

To verify the space savings achieved by the invention, two compact circuit board layouts have been implemented. Fig. 5 shows the circuit board layout proposed by Cruz et al., Which is shown in Fig. 1. Fig. 6 shows the circuit board layout of the converter according to the invention. As can be seen, the circuit of the invention can be placed on a smaller circuit board surface, which provides cost savings and reduces the overall size of the converter.

Since the electrical stress on the elements during conversion is reduced, it is possible to increase the switching frequency of the converter and thereby improve the generated waveforms. Any of the PWM (pulse width modulation) control methods for three-phase three-level "" boost "° (voltage multiplier) type of converter can be used to control input currents and output voltages. Such a control method is described in [R. Rojas, ”Method and Circuit of Control For Recti fi cador of Tipo Elevador Trifásico de Três Niveis-Patent PI 9907351-0]. Fig. 7 shows a circuit diagram of a converter according to an alternative embodiment of the invention. As can be seen from Fig. 7, this circuit is in principle equal to the circuit in Figs. 2.

However, in each snubber circuit, the anode of the second snubber diode D12, D22, D32 is connected directly to the terminal 5 of the second snubber inductor, and the anode of the tenth snubber diode D14, D24, D34 is connected directly to the fourth snubber capacitance C14, C24, C34 and snubber diodes D16, D26, D36 cathode. The absence of the second C12, C22, C32 and third C13, C23, C33 snubber capacitances and the third D13, D23, D33 and the fifth D15, D25, D35 snubber diodes will result in a snubber circuit which will only reduce the losses at the moment of attack, ie. reduce the current increase at the moment of switching on. The losses due to the switch-off of the switch will not be reduced in this case.

Fig. 8 shows: a simplified diagram of a three-phase, three-level "boost" (voltage multiplier) type of converter with a passive snubber according to another embodiment of the invention. The converter is connected to two loads LD1 and LD2, of which one LD1 between the first terminal P and the center point M, and the second LD2 between the second terminal N and the center point. The loads LD1 and LD2 should be substantially symmetrical, but the arrangement allows a slight asymmetry in the loads.

Claims (2)

1. 0 15 20 25 30 15 a | ø o - ». a. . n n PATENT REQUIREMENTS. Converter arranged to be connected to a three-phase input voltage system (V1, V2, V3), comprising a first terminal (P) and a second terminal (N) of a direct voltage output arranged to be connected to at least one load (LD), a center point (M), arranged to constitute a reference for a positive and negative voltage at the DC output, and, for each phase of the input system, a first saving diode (DB 1, DB2, DB3) and a second saving diode (DB2, DB4; DB6 ), whose cathodes are connected to the first terminal of the DC voltage output (P) and the respective phase of the input voltage system (V1, V2, V3), and whose anodes are connected to the respective phase of the input voltage system (V1, V2, V3) and the second terminal of the DC voltage output ( N), a switch (S1, S2, S3) connected to the center point (M) and arranged to go through a switch process, a snubber circuit (1, 2, 3) connected to the first terminal (P) and the second terminal (N) and including means for storing and transferring energy i, which is formed during the switching process, to the load (LD), characterized in that said means for storing and transmitting to the load (LD) the energy formed during the switching process comprises a snubber inductor (L111, L12, L13), wherein a first connection terminal (4) for the snubber inductor is connected to the respective phase of the input voltage system (V1, V2, V3), and wherein a second connection terminal (5) for the snubber inductor is connected to the switch (S1, S2, S3). The transducer of claim 1, wherein each snubber circuit (1, 2, 3) further comprises a first snubber diode (D11, D21, D31), a second snubber diode (D12, D22, D32), a fourth snubber diode (D14, D24, D34), a sixth snubber diode (D16, D26, D36), a first snubber capacitance (C11, C21, C31), and a fourth snubber capacitance (C14, C24, C34), characterized in that 1524 The cathode of the second snubber diode (D12, D22, D32) is connected to the anode of the first snubber diode (D11, D21, D31), and the anode of the second snubber diode (D12, D22, D32) is connected to the second connection terminal (5 ) on the snubber inductor, the first snubber capacitance (C11, C21, C31) is connected between on the one hand the first connection terminal (4) of the snubber inductor and on the other hand the anode of the first snubber diode (D11, D21, D31) and the second snubber cathode of the diode (D12, D22, D32), the cathode of the first snubber diode (D11, D21, D31) is connected to the first terminal (P) of the DC voltage output, the fourth snubber diode its (D14, D24, D34) cathode is connected to the second connection terminal (5) of the snubber inductor, the fourth snubber capacitance (C14, C24, C34) is connected between one side the first connection terminal (4) of the snubber inductor and on the other hand the anode of the fourth snubber diode (D14, D24, D34) and the cathode of the sixth snubber diode (D16, D26, D36), and the anode of the sixth snubber diode (D16, D26, D36) are connected to the second terminal (N) of the DC voltage output. . A transducer according to claim 2, in which means for storing and transmitting to the load (LD) energy generated in the switching process comprises a second (C12, C22, C32) and a third (C13, C23, C33) snubber capacitance, and each snubber circuit further comprising a third snubber diode (D13, D23, D33), a fifth snubber diode (D15, D25, D35), in which: the anode of the third snubber diode (D13, D23, D33) is connected to the second connection terminal (5) on the snubber inductor, the second snubber capacitance (C12, C22, C32) is connected between the center (M) on one side and the cathode of the third snubber diode (D13, D23, D33) and the anode of the other snubber diode (D12, D22, D32) on the other hand, 10 15 e .. n. Qo en nu 1 a; of n. n i o: n. g,. ur n v u <a i a. n o n v c: - - ~ | | n e | a: 17 the third snubber capacitance (C13, C23, C33) is connected between the center (M) on one side and the anode of the fourth snubber diode (D14, D24, D34) and the cathode of the fifth snubber diode (D15, D25, D35) on the other , and the fifth snubber diode (D15, D25, D35) anode is connected to the cathode of the sixth snubber diode (D16, D26, D36) and the fourth snubber capacitance (C14, C24, C34). . Converters according to claims 1, 2 or 3, wherein an additional inductor (L1, L2, L3) is connected between each phase of the input voltage system and the respective first saving diode (DB1, DB3, DB5) anode, the respective second saving diode (DB2, DB4 , DB6) cathode and the first terminal of the snubber inductor (Li 1, Liz, Liz). A converter according to claims 1, 2, 3 or 4, wherein a first output capacitance (C1) is connected between the first terminal (P) and the midpoint (M), and a second output capacitance (C2) is connected between the second terminal ( N) and the midpoint (M).