SE464266B - Saett att anordna ett laesminne foer utlaesning av revisionslaegesinformation i en integrerad krets - Google Patents

Saett att anordna ett laesminne foer utlaesning av revisionslaegesinformation i en integrerad krets

Info

Publication number
SE464266B
SE464266B SE8800144A SE8800144A SE464266B SE 464266 B SE464266 B SE 464266B SE 8800144 A SE8800144 A SE 8800144A SE 8800144 A SE8800144 A SE 8800144A SE 464266 B SE464266 B SE 464266B
Authority
SE
Sweden
Prior art keywords
memory
circuit
integrated circuit
revision
pattern
Prior art date
Application number
SE8800144A
Other languages
English (en)
Swedish (sv)
Other versions
SE8800144L (sv
SE8800144D0 (sv
Inventor
T L Haulin
Original Assignee
Ellemtel Utvecklings Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ellemtel Utvecklings Ab filed Critical Ellemtel Utvecklings Ab
Priority to SE8800144A priority Critical patent/SE464266B/sv
Publication of SE8800144D0 publication Critical patent/SE8800144D0/xx
Priority to EP88850404A priority patent/EP0325096B1/de
Priority to DE3850648T priority patent/DE3850648T2/de
Priority to US07/287,145 priority patent/US4975876A/en
Priority to CA000587490A priority patent/CA1327647C/en
Priority to JP606889A priority patent/JP2647180B2/ja
Publication of SE8800144L publication Critical patent/SE8800144L/
Publication of SE464266B publication Critical patent/SE464266B/sv

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44Indication or identification of errors, e.g. for repair
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B20/00Read-only memory [ROM] devices

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Tests Of Electronic Circuits (AREA)
SE8800144A 1988-01-18 1988-01-18 Saett att anordna ett laesminne foer utlaesning av revisionslaegesinformation i en integrerad krets SE464266B (sv)

Priority Applications (6)

Application Number Priority Date Filing Date Title
SE8800144A SE464266B (sv) 1988-01-18 1988-01-18 Saett att anordna ett laesminne foer utlaesning av revisionslaegesinformation i en integrerad krets
EP88850404A EP0325096B1 (de) 1988-01-18 1988-11-29 Verfahren und Anordnung zum Lesen eines Aktualisierungszustandsinformation in einer integrierten Schaltung
DE3850648T DE3850648T2 (de) 1988-01-18 1988-11-29 Verfahren und Anordnung zum Lesen eines Aktualisierungszustandsinformation in einer integrierten Schaltung.
US07/287,145 US4975876A (en) 1988-01-18 1988-12-21 Method for arranging a read-only memory for reading out updating status information in an integrated circuit
CA000587490A CA1327647C (en) 1988-01-18 1989-01-04 Method for arranging a read memory for reading out updating status information in an integrated circuit
JP606889A JP2647180B2 (ja) 1988-01-18 1989-01-17 集積回路の更新状態情報を提供しかつ調べる方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE8800144A SE464266B (sv) 1988-01-18 1988-01-18 Saett att anordna ett laesminne foer utlaesning av revisionslaegesinformation i en integrerad krets

Publications (3)

Publication Number Publication Date
SE8800144D0 SE8800144D0 (sv) 1988-01-18
SE8800144L SE8800144L (sv) 1989-07-19
SE464266B true SE464266B (sv) 1991-03-25

Family

ID=20371099

Family Applications (1)

Application Number Title Priority Date Filing Date
SE8800144A SE464266B (sv) 1988-01-18 1988-01-18 Saett att anordna ett laesminne foer utlaesning av revisionslaegesinformation i en integrerad krets

Country Status (6)

Country Link
US (1) US4975876A (de)
EP (1) EP0325096B1 (de)
JP (1) JP2647180B2 (de)
CA (1) CA1327647C (de)
DE (1) DE3850648T2 (de)
SE (1) SE464266B (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6219748B1 (en) 1998-05-11 2001-04-17 Netlogic Microsystems, Inc. Method and apparatus for implementing a learn instruction in a content addressable memory device
US6795743B1 (en) 2000-09-18 2004-09-21 Dell Products L.P. Apparatus and method for electronically encoding an article with work-in-progress information
US11934094B2 (en) 2021-03-23 2024-03-19 International Business Machines Corporation Mask fingerprint using mask sensitive circuit

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2545047C3 (de) * 1975-10-08 1978-09-21 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zur Herstellung eines Halbleiterfestwertspeichers
US4414665A (en) * 1979-11-21 1983-11-08 Nippon Telegraph & Telephone Public Corp. Semiconductor memory device test apparatus
US4451903A (en) * 1981-09-14 1984-05-29 Seeq Technology, Inc. Method and device for encoding product and programming information in semiconductors
JPS5853093A (ja) * 1981-09-22 1983-03-29 Fujitsu Ltd 半導体装置
JPS6145498A (ja) * 1984-08-08 1986-03-05 Hitachi Ltd 半導体集積回路装置
JP2580558B2 (ja) * 1985-04-26 1997-02-12 株式会社日立製作所 インタフェース装置

Also Published As

Publication number Publication date
JPH01225000A (ja) 1989-09-07
DE3850648T2 (de) 1994-10-27
JP2647180B2 (ja) 1997-08-27
SE8800144L (sv) 1989-07-19
CA1327647C (en) 1994-03-08
EP0325096A1 (de) 1989-07-26
SE8800144D0 (sv) 1988-01-18
EP0325096B1 (de) 1994-07-13
US4975876A (en) 1990-12-04
DE3850648D1 (de) 1994-08-18

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