SE458564B - PROVIDED TO TRANSFER A BINARY CODE AND CODE CARRIER BEFORE IMPLEMENTING THE SET - Google Patents

Description

458 10 15 20 25 30 35 564 2 following portion of the same period depending on the value of said bit, and to inductively detect the signal addition in the code receiver.

With the code carrier according to the invention, which is of the type stated in the preamble of claim 2, the same object as above is achieved in that the memory is addressable by means of a first portion in each period of the periodic signal and that a pulse sensor connected to an output from the memory is controlled to in a second, subsequent portion of the same period of the periodic signal give it an addition depending on the bit value of the memory output.

In the preferred embodiment of the code carrier, the encoder comprises a pulse shaper connected to the memory output and a drive stage connected to the coil, which is controlled by the pulse shaper. Furthermore, the code carrier may have a counter for counting the number of received periods of the periodic signal and generating addresses for the addressing of the memory. The memory can also be switchable between reading and writing by means of a timing circuit for detecting a pause of a predetermined length in the periodic signal.

Preferred embodiments of the code carrier according to the invention as well as associated code receivers will be described in more detail in the following with reference to the accompanying drawings. Fig. 1 is a circuit diagram of a first embodiment of a code carrier according to the invention. Fig. 2 is a circuit diagram of an associated code receiver according to the invention. Fig. 3 is a circuit diagram of a second, reprogrammable embodiment of the code carrier according to the invention. Fig. 4 is a circuit diagram of a code receiver, which is intended for the code carrier shown in Fig. 3. Figures 5, 6 and 7 are diagrams showing waveforms occurring in the circuits shown in Figures 1-4.

A code bearer shown in Fig. 1 has a coil L1, via which the code bearer inductively receives and outputs signals to a code receiver shown in Fig. 2. The coil L1 is connected via a resistor R1 over a network of two capacitors C1 and C2 and two diodes D1 and D2 connected to ground earth. This network acts as a voltage doubling and rectifying network and generates a supply voltage to the code receiver over a voltage limiting zener diode Z1.

The coil L1 is also connected via the capacitor C1 to a second rectifying network, which consists of a diode D3, a capacitor C3 and a resistor R2. At the output of this rectifying network, a Schmidt trigger S1 is connected.

Via the capacitor C1, the coil L1 is also connected to a second Schmidt trigger S2, the output of which is partly connected to an input of an AND gate G1, and partly connected to the clock input of a counter PR1, the output of which is high after 16 received pulses at the clock input and is connected to the gate's second gate Gl.

The gate G1 output is connected to an input of a NAND gate G2, the output of which is connected to an input of a counter PR2. The output of the Schmidt trigger S1 is connected to the reset input of the counter PR1, the reset input to the counter PR2 and to the second input of the gate G2.

Of the counters' PR2 outputs, three are connected to inputs to a 1/8 decoder A, the outputs of which together with the counter PR2's other inputs constitute address inputs to a memory M, which has one corresponding to the product of the number of inputs from counter PR2 and the number of inputs from decoder A. number of bit cells. The bit value of the memory cell in the memory M addressed at each time by the counter PR2 and the decoder A appears at an output of the decoder A, which output is connected to an input of an AND gate G3, the second input of which is connected to the output of the gate G2.

The output of the gate G3 is connected to the input of a first pulse shaper P1, which is constituted by a mono-stable flip-flop and serves as a delay circuit. The output from the pulse shaper P1 is connected to the input of a second pulse shaper P2, which also consists of a monostable flip-flop. The output of the pulse shaper P2 is connected to the base of a transistor T1, which is connected between the positive supply voltage and the connection of the coil L1 to the resistor R1.

Before describing the function of the code carrier in Fig. 1, the construction of the code receiver in Fig. 2 will also be described.

The code receiver in Fig. 2 consists of an oscillator part and a detector part. The oscillator part includes an oscillator 0, the output of which is connected to a counter PR3, the outputs of which are connected to a combinatorial network Kl.

Two outputs from the combinatorial network, on which outputs inverse signals appear, are connected via drive stages F1, F2 to a coil L2. On a third output from the combinatorial network, a clock signal appears, which is used for clocking the signals obtained from the detector part of the code receiver.

More specifically, the detector part consists of a coil L3 with a central socket, which is connected to circuit earth.

One end of the coil L3 is connected via a diode D4 to an input of a comparator J1, and the other end of the coil L3 is connected via a diode DS to the other input of the comparator J1. The first input of the comparator J1 is disconnected to circuit earth via a resistor R3, while the second input of the comparator J1 is disconnected to circuit earth via a resistor R4 and a capacitor C4. The output of the comparator J1 is connected to the input of a pulse shaper P3, which is constituted by a monostable flip-flop, and the output of the pulse shaper P3 constitutes the data output of the code receiver, on which data is detected by clocking by the clock signal of the combinatorial network K1.

The operation of the circuits shown in Figs. 1 and 2 will now be described, it being assumed that the memory M contains a binary code of a plurality of bits, which code is to be detected by the code receiver in Fig. 2. Reference is also made to Figs. 5 and 7. To perform the code transmission, the code carrier, which is a separate unit, is placed in such a position relative to the code receiver that the coils L1, L2 and L3 are inductively connected to each other. The combinatorial network K1 generates a train of pulses, the number of which is equal to 16 plus the number of bits in the memory M. After this pulse train a pause is made, after which the same sequence is repeated again. The periodic signal thus induced in the coil L1 has a substantially sinusoidal shape and charges the capacitors C2 and C3 to a positive polarity, the capacitor C2 being responsible for the power supply of the code carrier. During a pause between the pulse trains, the voltage on the capacitor C3, the capacitance of which is substantially lower than the capacitance of the capacitor C2, drops sufficiently for the output signal on the Schmidt trigger S1 to change level, whereby the counter PR1 and the counter Pk2 are reset.

For each pulse following the first 16 pulses after the pause in the pulse train, the counter PR2 is advanced one step, so that all the bit cells of the memory M are consecutively addressed by the counter PR2 and the decoder A. The pulses appearing at the gate G2 output are used to clock out the decoder The bit values occurring at the output of the pulse shaper P1, which after a predetermined delay act on the pulse shaper P2, which in turn opens the transistor T1 for a predetermined time.

Fig. 5 shows at the top the appearance of the pulse train PT at the output of the Schmidt trigger S2 and at the bottom the appearance of a reset signal RS at the output of the Schmidt trigger S1 is shown. It can be seen that the reset signal RS changes level shortly after the start of the pause between the pulse bundles in the pulse train PT, the delay being dependent on the discharge of the capacitor C3.

The pulse train induced in the coil L1 has a substantially sinusoidal shape, as can be seen from Fig. 7. Fig. 7 shows the level at which the counters PR1 and PR2 are triggered, for example at a time to. The pulse length or time delay of the pulse shaper P1 is indicated as a time interval t1 458 564 10 15 20 25 30 35 6 in Eig 7 and the pulse length of the pulse shaper P2 is indicated as a time interval t2 in Fig. 7. If an addressed bit in the memory M results in a "1" at the output of the decoder A, the pulse shaper P1 will be triggered, so that the pulse shaper P2 is triggered by the delay time t1 after the time to. The pulse shaper P2 will thus make the transistor T1 conductive during a time interval t2, whereby the periodic signal induced in the coil L1 via the transistor T1 is given an addition during said interval t2, which addition in Fig. 7 is indicated by a dashed line. As a result of this addition, the respective edge of the sine waveform will become steeper, which results in a higher voltage being induced in the half of the coil L3 in the decoder part of the code receiver which is connected between the circuit ground and the diode D4. Other positive half-periods of the sine wave in Fig. 7 result in the induction of a voltage in said half of the coil L3, which voltage is approximately as high as or preferably slightly lower than the voltage induced in the lower half of the coil L3 by the negative half-periods of the sine wave in Fig. 7. As a result, the voltage across the capacitor C4 in the decoder will correspond to just over half the peak-to-peak value of the sine signal in Fig. 7. This voltage on the capacitor C4 constitutes the reference voltage in the comparator J1. The higher voltage induced in the upper half of the coil L3 due to the conduction of the transistor T1 during the interval t2 will thus be sensed by the comparator J1, the output signal of which then triggers: the pulse shaper P3, which then emits a pulse at the data output, which pulse is clocked out by the clock pulses at the clock output from the combinatorial network Kl. it will be appreciated that by the inventive embodiment of the code bearer and the code receiver, where the actual clock signal from the code receiver to the code bearer is also used for the information transmission from the code bearer to the code receiver, a very fast transmission method is provided. As an example, the pulse frequency in the pulse train PT may be 1 MHz, whereby transmission times per ten bits in the memory M of about 10 ps can be achieved.

Thus, according to the invention, a periodic signal in the form of the pulse train PT is supplied from the code receiver to the code carrier and in each period of the supplied periodic signal a bit of the code is transmitted from the code carrier to the code receiver by giving the code carrier supplied signal an addition depending on the value of said piece. The delivered signal addition is then detected in the code receiver. By counting the counters PR1 and PR2 at the first time t0, while the addition is given during a later time interval t2, the function is achieved that by means of a first portion in each period of the periodic signal a special memory cell is addressed, in which a bit in the code is stored, and that the supplement is given in a second, subsequent batch of the same period.

In the variant of the code carrier shown in Fig. 1, the code in the memory M is fixed and not reprogrammable. The embodiment of a code carrier according to the invention shown in Fig. 3 contains both the circuits made by the code carrier according to Fig. 1 and further circuits for making the memory M reprogrammable. The further circuit elements in the code carrier according to Fig. 3 are more specifically three gates G4, G5 and G6, two counters PR4 and PR5, two combinatorial networks K2 and K3, a bistable flip-flop V1 and a Schmidt trigger S3. The G5 gate is of the "tri-state" type. The code carrier in Fig. 3 further contains a decoder part, which substantially corresponds to the decoder part in the code receiver according to Fig. 2. It thus comprises a coil L4 with earthed central socket, which coil one end via a network consisting of a diode D6, a resistor RS and a zener diode Z2 is connected to one input of a comparator J2, while the other end of the coil L4 via a network, which consists of a diode D7, a resistor R6, a capacitor C5 and a zener diode Z3, is connected to the other input of the comparator J2.

The output of the comparator J2 is connected to the input of a pulse shaper P4, which is a monostable flip-flop. 458 564 10 15 20 25 30 35 8 The code receiver according to Fig. 4 contains the same components as the code receiver according to Fig. 2 and in addition a gate G7, two pulse shapers P5 and P6, a transistor T2 and a bistable flip-flop V2. The detector part of the code receiver is not shown in Fig. 4.

The mode of operation of the code carrier according to Fig. 3 and the code receiver according to Fig. 4 is the same as for the circuits according to Figs. 1 and 2, when a code is read out from the memory M in the code carrier.

To read a new code in the memory M, the following sequence is performed, referring also to Fig. 6. To convert the memory M from read to write, a signal must be applied to an input R / W to the memory M. This is achieved by switching the flip-flop V1. The adjustment of the rocker V1 is achieved by means of such a pulse train PT1 as shown at the top of Fig. 6. More specifically, a pause is made in the pulse train PT1 after the first 30 + 16 pulses therein.

The pulse train PT1 is generated by the combinatorial network K1 after a pulse at the input W of the flip-flop V2 has changed this.

After the first 16 pulses have been counted by the counter PR1, the following 30 pulses will be counted by the counter PR4, which upon reaching 30 pulses simultaneously with the occurrence of the reset signal RS1 at the output of the Schmidt trigger S1 via the combinatorial network K2 gives a setting signal to rocker Vl. The signal appearing at the output of the flip-flop V1 is applied to the input R / W of the memory M and switches the memory to the write mode. the signal at the output of the flip-flop V1 is also applied to the combinatorial network K3, whereby the reset signal from an output of the network K3 to the reset input of the counter PR5 is removed. The signal at the output of the flip-flop V1 is further applied to the gate G5 to open it and finally a blocking input to the pulse shaper P1, whereby pulses occurring during the programming process at the output of the gate G3 are not passed to the transistor T1.

Q When the counter PR4 has counted 30 pulses, the combinatorial network K2 at one of its outputs also generates a signal which is applied to the second input of the gate G4 and blocks further supply of pulses to the counter PR4. In order to prevent the counter PR4 from continuing to count the pulses incoming to the coil L1 during the writing cycle, the output signal of the flip-flop V1 is also output to an input of the combinatorial network K2, whereby the counter PR4 is locked in its position. During the pause, the counters PR1 and PR2 are reset. The first 16 pulses after the pause are recalculated by the counter PRI, which then opens the gate Gl. Then the counter PR2 is supplied with as many pulses as the number of bits in the memory M. The reading of the new data in the memory M takes place via the output of the decoder A, which also serves as an input. This data is fed to the code carrier in the following manner. More specifically, the code to be programmed into the memory M is applied to the data input of the code receiver in Fig. 4 and clocked by the clock signals from the combinatorial network K1 through the gate G7 via the pulse shapes P5 and P6, which correspond to the pulse shapes P1 and P2 in the code carrier T2. , which corresponds to the transistor T1 in the code carrier. Thus, in the substantially sinusoidal signal applied to the coil L2, an addition is obtained in each period of this signal, which addition corresponds to, for example, a binary value "1".

The signal through the coil L2 can thus have substantially the appearance shown in Fig. 7. The signal is induced in the code carrier coil L4 and is applied to the comparator J1, so that the pulse shaper P4 generates a pulse sequence corresponding to the code, which is introduced via gate G5 and decoder A into memory M for writing the new code.

The counter PR5 counts during the enrollment the number of clock pulses supplied to the counter PR2 and will emit a blocking signal at its output connected to an input of the gate G2, when the number of pulses counted by the counter PR5 is equal to the number of bit cells in the memory M. At the same time the combinatorial network K3 an output signal via gate G6 to a programming input to the memory M. 458 10 15 20 25 30 564 10

After a predetermined burn-in time, when the new code in the memory M is permanently stored in it, the flip-flop V2 is reset in the code receiver. This is done in particular by the combinatorial network K1 at its output, which is connected to the reset input of the flip-flop V2, emits a signal for resetting the flip-flop V2. Hereby the code receiver in Fig. 4 is transmitted to the read mode. A relatively long pause in the pulse train transmitted via the coil L2 is now also made. In this case, first the Schmidt trigger S1 will generate its reset signal RS1 and then the Schmidt trigger S3 will generate its reset signal RS2. This resets the flip-flop V1 to its initial state, whereby the memory M is transferred to the read mode, the gate G5 is blocked, the counter PR5 is reset and the blocking of the counter PR4 ceases. As can be seen from the above, the code carrier according to the invention is advantageous in that it allows a very fast transmission of information, in that it is self-sufficient and in that it can be made programmable.

Finally, it should be noted that further modifications of the above-described code carriers are possible within the scope of the invention. Thus, although an inductive coupling between the code bearer and the code receiver is currently preferred, other forms of signal transmission between code bearers and code receivers are also conceivable.

Likewise, the signal addition from the transistor T1 or T2 can be made negative or located elsewhere in the period.

Claims (5)

10 15 20 25 30. ' 458 564 11 PATENT REQUIREMENTS A method of transmitting a binary code of a plurality of bits from a code carrier to a code receiver, wherein a periodic signal is applied inductively from the code receiver to the code carrier, characterized by the measures of inductively transmitting in each period of the inductively supplied periodic signal a bit in the code from the code bearer to the code receiver by addressing by means of a first portion in each period of the periodic signal a particular memory cell in the code bearer, in which memory cell a bit in the code is stored, and giving that code carrier inductively applied to the signal a second in a second , subsequent batch of the same period depending on the value of said bit, and to inductively detect the signal addition in the code receiver. Code carrier for transmitting a binary code stored therein of a plurality of bits to a code receiver, which is arranged to inductively supply a periodic signal to a sequentially addressable memory (M) in the code carrier with a number of bit cells corresponding to the number of bits in the code. , characterized in that the memory (M) is addressable by means of a first portion in each period of the periodic signal and that a pulse sensor (P1, P2, T1) connected to an output lwu from the memory is controlled to in a second, subsequent batch of the same period of the periodic signal give this an addition depending on the bit value of the memory output. 3. A code carrier as claimed in Claim 2, characterized in that it is inductively connected to the code receiver via a single coil (L1). 4. A code carrier as claimed in Claim 3, characterized in that the encoder (P1, P2, T1) comprises a pulse shaper (P1, P2) connected to the memory output and a drive stage (T1) connected to the coil (L1). which is controlled by the pulse shaper. 458 564 1 12 Code carrier according to one of Claims 2 to 4, characterized in that the memory (M) is switchable between reading and writing by means of a time circuit (PR4) for detecting a pause of a predetermined length in the periodic table. the signal.