SE445269B - Dator med indexerat lokalt direktminne - Google Patents

Dator med indexerat lokalt direktminne

Info

Publication number
SE445269B
SE445269B SE8107831A SE8107831A SE445269B SE 445269 B SE445269 B SE 445269B SE 8107831 A SE8107831 A SE 8107831A SE 8107831 A SE8107831 A SE 8107831A SE 445269 B SE445269 B SE 445269B
Authority
SE
Sweden
Prior art keywords
signals
memory
address
register
central processor
Prior art date
Application number
SE8107831A
Other languages
English (en)
Swedish (sv)
Other versions
SE8107831L (sv
Inventor
A B Barrow
H H Tsiang
Original Assignee
Wang Laboratories
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wang Laboratories filed Critical Wang Laboratories
Publication of SE8107831L publication Critical patent/SE8107831L/
Publication of SE445269B publication Critical patent/SE445269B/sv

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
SE8107831A 1980-12-29 1981-12-29 Dator med indexerat lokalt direktminne SE445269B (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/220,902 US4410941A (en) 1980-12-29 1980-12-29 Computer having an indexed local ram to store previously translated virtual addresses

Publications (2)

Publication Number Publication Date
SE8107831L SE8107831L (sv) 1982-06-30
SE445269B true SE445269B (sv) 1986-06-09

Family

ID=22825488

Family Applications (1)

Application Number Title Priority Date Filing Date
SE8107831A SE445269B (sv) 1980-12-29 1981-12-29 Dator med indexerat lokalt direktminne

Country Status (11)

Country Link
US (1) US4410941A (ko)
JP (1) JPS57135493A (ko)
BE (1) BE891653A (ko)
CA (1) CA1165898A (ko)
CH (1) CH657218A5 (ko)
DE (1) DE3151745A1 (ko)
FR (1) FR2497374B1 (ko)
GB (1) GB2090448B (ko)
IT (1) IT1145635B (ko)
NL (1) NL192144C (ko)
SE (1) SE445269B (ko)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4464713A (en) * 1981-08-17 1984-08-07 International Business Machines Corporation Method and apparatus for converting addresses of a backing store having addressable data storage devices for accessing a cache attached to the backing store
US4525778A (en) * 1982-05-25 1985-06-25 Massachusetts Computer Corporation Computer memory control
JPS6047624B2 (ja) * 1982-06-30 1985-10-22 富士通株式会社 アドレス変換制御方式
US4513371A (en) * 1982-07-29 1985-04-23 Ncr Corporation Computer interface apparatus using split-cycle lookahead addressing for faster access to paged memory
US4926316A (en) * 1982-09-29 1990-05-15 Apple Computer, Inc. Memory management unit with overlapping control for accessing main memory of a digital computer
US4524415A (en) * 1982-12-07 1985-06-18 Motorola, Inc. Virtual machine data processor
USRE37305E1 (en) * 1982-12-30 2001-07-31 International Business Machines Corporation Virtual memory address translation mechanism with controlled data persistence
DE3300223A1 (de) * 1983-01-05 1984-07-05 Siemens AG, 1000 Berlin und 8000 München Anordnung zur umwandlung einer virtuellen adresse in eine physikalische adresse fuer einen in seiten organisierten arbeitsspeicher einer datenverarbeitungsanlage
US4580217A (en) * 1983-06-22 1986-04-01 Ncr Corporation High speed memory management system and method
US4538241A (en) * 1983-07-14 1985-08-27 Burroughs Corporation Address translation buffer
US4747043A (en) * 1984-02-10 1988-05-24 Prime Computer, Inc. Multiprocessor cache coherence system
US4669043A (en) * 1984-02-17 1987-05-26 Signetics Corporation Memory access controller
US4873629A (en) * 1984-06-20 1989-10-10 Convex Computer Corporation Instruction processing unit for computer
US4757438A (en) * 1984-07-12 1988-07-12 Texas Instruments Incorporated Computer system enabling automatic memory management operations
EP0182501A3 (en) * 1984-11-20 1988-01-20 Tektronix, Inc. Memory mapping method and apparatus
EP0452991A3 (en) * 1985-05-29 1992-04-15 Kabushiki Kaisha Toshiba Cache system adopting an lru system
US4972338A (en) * 1985-06-13 1990-11-20 Intel Corporation Memory management for microprocessor system
US4698749A (en) * 1985-10-18 1987-10-06 Gte Communication Systems Corporation RAM memory overlay gate array circuit
JPH0814803B2 (ja) * 1986-05-23 1996-02-14 株式会社日立製作所 アドレス変換方式
US4930065A (en) * 1987-08-20 1990-05-29 David Computer Corporation Automatic data channels for a computer system
US4937736A (en) * 1987-11-30 1990-06-26 International Business Machines Corporation Memory controller for protected memory with automatic access granting capability
US5155834A (en) * 1988-03-18 1992-10-13 Wang Laboratories, Inc. Reference and change table storage system for virtual memory data processing system having a plurality of processors accessing common memory
US5155826A (en) * 1988-12-05 1992-10-13 Fadem Richard J Memory paging method and apparatus
US5099415A (en) * 1989-02-15 1992-03-24 International Business Machines Guess mechanism for virtual address translation
US5644787A (en) * 1993-08-03 1997-07-01 Seiko Epson Corporation Apparatus for controlling data transfer between external interfaces through buffer memory using table data having transfer start address transfer count and unit selection parameter
US5479628A (en) * 1993-10-12 1995-12-26 Wang Laboratories, Inc. Virtual address translation hardware assist circuit and method
US5842225A (en) * 1995-02-27 1998-11-24 Sun Microsystems, Inc. Method and apparatus for implementing non-faulting load instruction
US5838893A (en) 1996-12-26 1998-11-17 Microsoft Corporation Method and system for remapping physical memory
US5956754A (en) * 1997-03-03 1999-09-21 Data General Corporation Dynamic shared user-mode mapping of shared memory
KR100546403B1 (ko) * 2004-02-19 2006-01-26 삼성전자주식회사 감소된 메모리 버스 점유 시간을 가지는 시리얼 플레쉬메모리 컨트롤러
US7506009B2 (en) * 2005-01-28 2009-03-17 Dell Products Lp Systems and methods for accessing a shared storage network using multiple system nodes configured as server nodes
GB0505289D0 (en) * 2005-03-15 2005-04-20 Symbian Software Ltd Computing device with automated page based rem shadowing and method of operation
US20070039060A1 (en) * 2005-08-12 2007-02-15 Jamieson Georges E Methods and systems for programming secure data into programmable and irreversible cells
US9588902B2 (en) * 2012-12-04 2017-03-07 Advanced Micro Devices, Inc. Flexible page sizes for virtual memory

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3829840A (en) * 1972-07-24 1974-08-13 Ibm Virtual memory system
JPS51115737A (en) * 1975-03-24 1976-10-12 Hitachi Ltd Adress conversion versus control system
US3976978A (en) * 1975-03-26 1976-08-24 Honeywell Information Systems, Inc. Method of generating addresses to a paged memory
JPS52149444A (en) * 1976-06-08 1977-12-12 Fujitsu Ltd Multiplex virtual space processing data processing system
DE2641722C3 (de) * 1976-09-16 1981-10-08 Siemens AG, 1000 Berlin und 8000 München Hierarchisch geordnetes Speichersystem für eine datenverarbeitende Anlage mit virtueller Adressierung
JPS53121538A (en) * 1977-03-31 1978-10-24 Fujitsu Ltd Information processor

Also Published As

Publication number Publication date
NL192144B (nl) 1996-10-01
FR2497374A1 (fr) 1982-07-02
DE3151745A1 (de) 1982-08-19
JPS57135493A (en) 1982-08-21
NL192144C (nl) 1997-02-04
CH657218A5 (de) 1986-08-15
JPH0425579B2 (ko) 1992-05-01
BE891653A (fr) 1982-04-16
IT8168706A0 (it) 1981-12-29
FR2497374B1 (fr) 1988-05-06
CA1165898A (en) 1984-04-17
GB2090448B (en) 1984-11-28
DE3151745C2 (ko) 1991-05-16
GB2090448A (en) 1982-07-07
US4410941A (en) 1983-10-18
IT1145635B (it) 1986-11-05
NL8105849A (nl) 1982-07-16
SE8107831L (sv) 1982-06-30

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