SE421852B - Flerskiktig dektronisk skiktkrets och forfarande for dess framstellning - Google Patents

Flerskiktig dektronisk skiktkrets och forfarande for dess framstellning

Info

Publication number
SE421852B
SE421852B SE7606715A SE7606715A SE421852B SE 421852 B SE421852 B SE 421852B SE 7606715 A SE7606715 A SE 7606715A SE 7606715 A SE7606715 A SE 7606715A SE 421852 B SE421852 B SE 421852B
Authority
SE
Sweden
Prior art keywords
layer
dectronic
procedure
preparation
circuit
Prior art date
Application number
SE7606715A
Other languages
English (en)
Swedish (sv)
Other versions
SE7606715L (sv
Inventor
K Breuninger
D Haberland
B Strasser
A Weitze
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of SE7606715L publication Critical patent/SE7606715L/xx
Publication of SE421852B publication Critical patent/SE421852B/xx

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • H05K3/4667Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders characterized by using an inorganic intermediate insulating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
SE7606715A 1975-06-13 1976-06-11 Flerskiktig dektronisk skiktkrets och forfarande for dess framstellning SE421852B (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2526553A DE2526553C3 (de) 1975-06-13 1975-06-13 Mehrlagige elektronische Schichtschaltung und Verfahren zu ihrer Herstellung

Publications (2)

Publication Number Publication Date
SE7606715L SE7606715L (sv) 1976-12-14
SE421852B true SE421852B (sv) 1982-02-01

Family

ID=5949067

Family Applications (1)

Application Number Title Priority Date Filing Date
SE7606715A SE421852B (sv) 1975-06-13 1976-06-11 Flerskiktig dektronisk skiktkrets och forfarande for dess framstellning

Country Status (9)

Country Link
JP (2) JPS5210569A (xx)
AT (1) AT359583B (xx)
CH (1) CH604344A5 (xx)
DE (1) DE2526553C3 (xx)
FR (1) FR2314585A1 (xx)
GB (1) GB1540112A (xx)
IT (1) IT1063970B (xx)
NL (1) NL7604158A (xx)
SE (1) SE421852B (xx)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991011025A1 (en) * 1990-01-16 1991-07-25 A.S Micro Electronics A method for manufacturing of mineature impedance matched interconnection patterns

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2045540B (en) * 1978-12-28 1983-08-03 Tdk Electronics Co Ltd Electrical inductive device
EP0062084A1 (en) * 1981-04-06 1982-10-13 Herbert Irwin Schachter Multi-level circuit and method of making same
US4495479A (en) * 1982-10-22 1985-01-22 International Business Machines Corporation Selective wiring for multilayer printed circuit board
JPS60130883A (ja) * 1983-12-19 1985-07-12 中央銘板工業株式会社 多層印刷配線板
DE3831148C1 (xx) * 1988-09-13 1990-03-29 Robert Bosch Gmbh, 7000 Stuttgart, De

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991011025A1 (en) * 1990-01-16 1991-07-25 A.S Micro Electronics A method for manufacturing of mineature impedance matched interconnection patterns

Also Published As

Publication number Publication date
CH604344A5 (xx) 1978-09-15
JPS5210569A (en) 1977-01-26
FR2314585A1 (fr) 1977-01-07
DE2526553C3 (de) 1978-06-01
IT1063970B (it) 1985-02-18
DE2526553B2 (de) 1977-09-29
SE7606715L (sv) 1976-12-14
JPS5731876U (xx) 1982-02-19
ATA358776A (de) 1980-04-15
GB1540112A (en) 1979-02-07
NL7604158A (nl) 1976-12-15
DE2526553A1 (de) 1976-12-16
AT359583B (de) 1980-11-25
FR2314585B1 (xx) 1979-09-28

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