RU97U1 - LAN controller - Google Patents

Abstract

A local area network controller comprising a processor, random access memory, read-only memory, transceiver, respectively connected to a trunk, which is connected to a common bus through the M / OS interface unit, characterized in that, in order to increase reliability, control decoder is introduced into it sums, an indication unit, the outputs of the checksum decoder being connected respectively to the M / OS interface unit, a processor, random access memory, a transceiver, an in dictations.

Description

LAN controller

The utility model relates to controllers of local computing networks (LAN).

The Internet network of the intellectual network is known (patent Е1ГВ 04IC3I4 class. 6-OfiF 13/12, 91) containing the main processor, communication channel, protocol machine, controller, shared memory.

The disadvantage of this device is the low reliability, which translates into the impossibility of the device without failures in continuous mode (24 hours a day).

The closest implementation to the functions and method is the LAN controller (Local area networks E.V. Boychenko, V. Kalfa, V.V. Ovchinnikov, Moscow, and communications, 1985, p. 146, Fig. 9.6 - prototype) comprising a processor element, random access memory, read-only memory device, a unit for interfacing with a mono channel cable, a unit for interfacing with a common line, connected to the line, and common.

The disadvantage of this controller is the reliability.

Consider this as an example.

As a result of a rather long operation in conditions of strong industrial interference (both on the power supply and on the air) of the local area network controller (IOIC) built on the prototype circuit, the following typical situations arise, leading to failure:

unforeseen incorrect access to the network controller both from the side of the Common Bus (PC), and from the side of the mono channel;

random reading by the processor of the controller from the ROM of the programs of an erroneous code of a data command;

/ -5GK application 93-034351 / 24

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interfering and thermomodulating effects of one of the controller's rooms on others.

This all causes the network controller to go into an unused :: state and, as a result, ult:

-in the best, loss to devices on the local network from the side (PC),

- in the worst case, blocking the operation of all network devices (due to incorrect handling of the network controller),

The purpose of the utility model is to increase the reliability of the LAN controller.

This goal is achieved by the fact that in the controller of the local area network containing the processor, VCA, ROM, transceiver, respectively connected to the highway, which through the M / OS interface unit is connected to the common SHROSHA, checksum decoder, indication unit are introduced, and the outputs of the control decoder the sums are connected to the conjugation unit L1 / OI, processor, RAM, transceiver, indication unit.

In this way, introducing the checksum decoder into the device, the display unit and connecting them in the appropriate way, they achieve increased controller reliability. This occurs for the following reasons:

I. An additional independent device for analyzing the correct execution of individual 1 functions by the processor appeared in the controller (counting the checksum of ROM programs, reading the packet to be transferred from the buffer RAM, transmitting the packet to the network and receiving a response from the network, writing the received packet to the buffer RAM, issuing an interrupt on a PC). This is desh / 1frat13r checksums.

the execution of the next function is performed only if the two devices (the CS decoder and the processor) independently of each other decide on the admissibility of this transition. If, for some reason, the processor didn’t fail and the next function was performed incorrectly (for example, reading a packet from the buffer control), the KS decoder will not have permission to execute the next step, which will cause the fuzzy - the packet will be transmitted, and incorrect information will thus not get into network.

2. The indicator of the indicator block indicates at least one case of incorrect execution by the processor of the corresponding specific function for the entire period of the network controller’s operation from the inclusion of it. This allows you to quickly identify weaknesses in the controller, including the processor itself and also quickly eliminate them.

3.Each broadcast session 1M: 1 begins with the installation of the processor

to the initial state by applying a RESET signal from the side of the PC. In this case, initialization of all internal and external resources of the processor takes place and the execution of a sequence of functions begins. So Qcm. during operation, the network controller as a result of some external or internal reasons freezes, the next start from the OS side will bring it out of this state, and the session

Communication will begin under normal initial conditions.

.2. On the . presents a block diagram of the device.

The local area network controller (Fig.) Contains processor I, random access memory (VCA) 2, read-only memory (ROM) 3, transceiver 4, connected in a corresponding way 1CH / 1M to highway 5, which is connected to a common interface M / OSh S bus 7, deshgr fractor control su mm 8, the outputs of which are connected to the processor I, OVU 2, transceiver 4,

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The LAN controller operates as follows: PC:

1. Loads into the buffer IED 2 the package of information to be transferred. Processor I at the same time: is dressed in a reset state, and all its conclusions are in the third state.

2. Starts processor I by removing the RESET signal from it.

CPU I:

1.Prom1 initiates the initialization of all external and internal resources.

2. To calculate the control sum (Cs) of the ROM of 3 programs (this checks the reliability of the processor itself).

3.Puts out the calculated KS for analysis to the KS8 decoder

- if the calculated CS matches the specified one, permission to continue work is set from processor K8 to processor I, and permission to access ner / iy from processor I is set to buffer IED 2,

- otherwise, the processor I is muffled and the Ready indicator of the processor of the indication unit 9 goes out.

4. Reads the packet to be transferred from the buffer RAM 2 to the resident memory.

5.Calculates the checksum of the packet.

6. Puts out the calculated KS for analysis to the KS8 decoder.

- if the calculated COP matches the given one, the KC8 decoder:

a) sets the permission to work on transceivers 4

b) sets the Packet Ready flag to processor I

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) turns off the Packet Ready indicator,

c) does not set the Packet Ready flag on the processor,

In this case, trawling will be prohibited both physically (ban on transceivers 4) and programmatically (ban on processor I).

7. Transmits the packet to the network and receives a response from the network.

8.Counts the COP of the received packet and writes it to the decoder KS8

- if the calculated CS matches the specified one (standard for the given network), the CS decoder sets the write permission to the buffer (WU 2 of the received packet and permission to pass the interrupt unit from processor I / OS 6 to the processor I

- otherwise, permissions are not set by the KS8 decoder and the Network accuracy indicator on the indicating unit 9 goes out.

9. Writes the packet received from the network to the buffer VCA 2 and issues an interrupt to the PC. Interruption tells the PC about the following:

- the broadcast session on the network went fine,

-in the buffer RAM is information received from network devices.

If for some reason the interruption is not set (due to the fault of the controller or the network itself), the PC, after waiting a certain time, restarts the controller, thereby initiating a retransmission.

Compiled by S.Vlasgok

Claims (1)

A local area network controller comprising a processor, random access memory, read-only memory, transceiver, respectively connected to a trunk, which is connected to a common bus through the M / OS interface unit, characterized in that, in order to increase reliability, control decoder is introduced into it sums, an indication unit, the outputs of the checksum decoder being connected respectively to the M / OS interface unit, a processor, random access memory, a transceiver, an in dictations.