RU50018U1 - DATA TRANSMISSION MULTIPLEXOR - Google Patents

Abstract

This technical solution relates to the field of digital computing and data transmission, namely, to systems for processing radar information, and can be used as part of control centers. The data transmission multiplexer (BR21-407 module) is a data transmission equipment (APD) operating in the codes of the ASPD-U equipment (DEI3.031.000), T-235-1L equipment (LT1.600.012), products 1L110, 1L15 and 9S520, and also the controller of navigation equipment TNA-4. The module is designed for simultaneous independent data exchange with ASPD-U equipment (or block C51 DEI2.000.004), T-235-1L equipment via a radio channel formed by the P163-50U radio station and P163-UP radio receiver, or via a wired communication channel. The module is designed to transmit information to the 9C520 product via a wired communication channel. The module is designed to ensure the interaction of an electronic computer (computer) with equipment TNA-4. A communication channel can be formed:

- “Crossbow” type radio equipment (tonal frequency channel);

- field telephone cable type P274M (wired channel);

- telephone cable type P269 or PTRK (wired channel).

Pairing with a computer via the ISA bus.

The module consists of the following functional devices:

- Telecode data transmitter working in the codes of the ASPD-U equipment;

- Telecode data receiver operating in the codes of the ASPD-U equipment;

- Telecode data transmitter operating in hardware codes T-235-1L;

- Telecode data receiver operating in hardware codes T-235-1L;

- Telecode data transmitter operating in the codes of the 9C520 module;

- TNA-4 navigation equipment controller;

- a node for interfacing a module with the ISA computer system bus (interrupt controller, information writing / reading control circuit);

- Telecode transceiver in codes T-235-1L (radio). Structurally, the module is implemented on a single-board design according to the Euromechanics standard, size 6U (260 x 180 x 20 mm).

Description

Technical field

This technical solution relates to the field of digital computing and data transmission, namely, to systems for processing radar information, and can be used as part of control centers.

State of the art

An analogue of this technical solution is the BI-PULSE SIGNAL CONVERSION DEVICE (certificate for utility model RU 24060 U1, application 2001131148 dated November 19, 2001, published July 20, 2002, bulletin No. 20, copyright holder of the Federal State Unitary Enterprise NPP Rubin, authors P. Kochegarov Yu., Shmyrev V.N.), containing a pair of pairing receivers, the input of which is connected to the first input of the device, a block of pairing transmitters, the output of which is connected to the first output of the device, a linear transmitter block, the output of which is connected to the second output of the device, a linear receiver block , entrance which is connected to the second input of the device, the bi-pulse signal encoder block, the first and second cat outputs are connected respectively to the input of the linear transmitter block and the first input of the pairing transmitters, the bi-pulse signal decoder block, the first and second of which are connected respectively to the third output of the bi-pulse signal encoder block and the output linear receiver unit, and the first output with a second input

a pair of interface transmitters, a clock generator unit with a divider, the first two outputs of which are connected respectively to the first input of the bi-pulse signal encoder block and the third input of the bi-pulse signal decoder, characterized in that the device further comprises a buffer block, three inputs of which are connected respectively to the input of the receiver block pairing, the output of the clock generator with a divider and the second output of the block of the decoder bi-pulse signal, and two outputs are connected respectively to the third input th transmitter block pair and the second input signals biimpulsnyh encoder block.

The disadvantages of this analogue are its small functionality, which does not allow for the exchange of information through a variety of communication channels and wired cable links to navigation systems.

Another analogue of this technical solution is a SPECIAL DEVICE FOR SIGNAL TRANSFORMATION (certificate for utility model RU 24061 U1, application 2001123484 dated 08.28.2001, published on 07.20.2002, bulletin No. 20, copyright holder of the Federal State Unitary Enterprise Rubin Scientific-Production Enterprise, authors Evseeva O.B., Degtyarev Yu.B.), containing a control unit consisting of a clock signal generator, an I / O port decoder, three inputs of which are connected to inputs A12-A0, IOR and IOW of the ISA device bus, recording control circuits in parallel-serial port block, the four inputs of which are connected inens, respectively, with the IOR, IOW and DO inputs of the ISA bus of the device and the first output of the I / O port decoder, and the first output with the D5 output of the ISA bus of the device, the interrupt circuit, the eleven outputs of which are connected respectively to the eleven outputs of the IRQ3-IRQ15 of the ISA device, a unit for matching output signal levels, the first and second groups of outputs of which are connected respectively with a first and second group of outputs of a control interface and a joint C2-SPEC device for connecting to special equipment, a unit for matching input levels with channels, the first and second groups of inputs of which are connected respectively to the third and fourth group of inputs of the control interface and the joint C2-SPEC device for connecting with special equipment, characterized in that the device further comprises a parallel-serial port block, the inputs of which are connected respectively to the output (CLK ) clock generator, output A4-A0 of the ISA device bus, two outputs (CS and CSIRQE) of the I / O port decoder, IOR and IOW outputs of the ISA device bus, second output (nConf) of the recording control circuit Lok parallel-serial port, input / output D7-D0 ISA bus device outputs block matching levels

the input signals, and the outputs are connected respectively to the fifth input (CND) of the write-control circuit of the parallel-serial port block, with two inputs of the IRQE (3-7, 9-12, 14, 15) and the IRQ of the interrupt circuit, with the inputs of the matching unit levels of output signals.

The disadvantage of this analogue is its limited functionality, which does not allow it to implement the transmission of information through various communication channels (wired and radio) with the required exchange algorithms and pairing with tank navigation equipment.

The closest analogue (prototype) of the claimed technical solution is a MULTIPLEXOR TELECOMMUNICATION MULTIFUNCTIONAL (patent for utility model RU 40509 U1, application 2004115534 from 05.25.2004, published September 10, 2004, bulletin No. 25, copyright holder of JSC NPP Rubin , authors Sokov M, V., Kochegarov P.Yu., Shmyrev V.N., Kalinina O.I., Zyabirova L.I., Sizov A.D., Oskin V.A.), built on the modular principle and comprising a system unit in which a four-channel telegraph unipolar module (M4TGO), a four-channel interface module C2 (M4C2), are located, the first a group of inputs and outputs of which is connected to buses C2 connecting to a physical line, a four-channel telegraph bipolar module (M4TGD), a first group of inputs and outputs of which is connected to buses C1-TG of connecting to telegraph communication channels, a two-channel bi-pulse module (M2BI), the first group of inputs -outputs of which is connected to buses С 1-I connecting to pulse channels, a single-channel bi-pulse module (М1БИ), the first group of inputs and outputs of which is connected to a bus С 1-I connections and bi-pulse channel, the module is single-channel the first telephone (М1ТЧ / ТФ), the first group of inputs / outputs of which is connected to the bus C1-ТЧ to connect to the telephone communication channel, as well as the adjustment and control unit (DBK) in a separate construct, the first group of inputs and outputs of which is connected to the first group of inputs the outputs of the four-channel telegraph unipolar (M4TGO) module, and the second group of inputs / outputs with C1-TGO buses connecting to telegraph communication channels, characterized in that the multiplexer further comprises m m structurally located in the system unit of the multiplexer moduli asynchronous four-channel adapter (MA4A), the first group of inputs-outputs being connected through an internal serial interface (FS) to a second group of four-input module outputs a unipolar telegraph (M4TGO) or four-joint module C2 (M4S2) or module

four-channel telegraph bipolar (M4TGD), or a two-channel bi-pulse module (M2BI), a single-channel bi-pulse module (M1BI) and a single-channel telephone module (M1ТЧ / ТФ), a group control board (CCP), the first group of inputs and outputs of which are connected via an internal parallel interface bus (VPRI) with groups of second inputs and outputs m of four-channel asynchronous adapter modules (MA4A), a interface card (PS), structurally located in the PC system unit, the first group of inputs and outputs of which are connected to the second second group of inputs-outputs of the group management board (PSU) and a second group of inputs-outputs connected to the system bus ISA personal electronic computer (PC) that is compatible with IBM PC.

The disadvantage of the prototype is the lack of functionality that does not allow for the transmission of information through communication channels using special equipment, as well as interfacing with navigation equipment.

The essence of the technical solution

The well-known data transfer multiplexer contains the ISA system bus of a specialized electronic computer, an interrupt controller connected via inputs to the IRQ1 - IRQ7 interrupt circuits from the device blocks and the IRQ output and data I / O with the ISA system bus, a read / write control circuit connected on the read and write circuits with the device blocks, on the DATA, ADDRESS I / O and W and R inputs with the ISA system bus.

The purpose of this technical solution is to expand the functionality, ensure data transfer through various communication channels (wired and radio) using special equipment algorithms, as well as interfacing with navigation equipment and topographic referencing tools.

To achieve this goal, the multiplexer further comprises DATA telecode receiver ASPD-U, ASPD-U telecode transmitter, T-235-1L telecode transmitter, T-235-1L telecode transmitter, and telecode transmitter (for 9c520 product) connected to the ISA system bus via DATA circuits , a controller for interfacing with the TNA-4 tank navigation equipment, moreover, the channel part of the telecode receivers and transmitters is connected to the communication channel, as well as the telecode

a transceiver in codes T-23 5-1L (radio), connected by input, output and control to a radio station R-163-50U and a radio receiver R-163-UP.

The ASPD-U telecode transmitter contains a crystal oscillator G, a PF bandpass filter, a digital-to-analog DAC converter, the first input of which is connected to the output of a PF bandpass filter, an amplifier U whose input is connected to the output of a digital-to-analog DAC converter, and an output transformer Tr, whose input is Tr is connected to the output of amplifier U, and the output is connected to the channel of the tone frequency of the PM, a programmable logic integrated circuit FPGA, which implements the amplitude register of the output signal PrA and the state register PrC, the inputs of which are connected are connected to the DATA and RECORDING circuits of the ISA bus, the FM phase modulator, the first input of which is connected to the output of the amplitude register of the output signal PrA, and the output to the second input of the DAC digital-to-analog converter, the frequency divider D, the two inputs of which are connected respectively to the output of the Prc status register and the output of the crystal oscillator G, and the first output - with the input of the bandpass filter PF, accumulating the counter with the decoder NS, the input of which is connected to the second output of the frequency divider D, and the first output - with the IR1 circuit of the ISA bus, two-port operational e RAM memory, the first input of which is connected to the second output of the accumulating counter with the NS decoder, and the second, third, fourth and fifth inputs are with the ISA bus READ, DATA, RECORD, ADDRESS circuits, the FCC correction signal generator, the input of which is connected to the output an accumulating counter with a NS decoder, a multiplexer, the three inputs of which are connected respectively to the DATA output of a dual-port random access memory RAM, the output of the correction signal generator FCC and the second output is accumulative a decoder counter with the NA, and an output - to a second input of the phase modulator PM.

The ASPD-U telecode receiver contains an input transformer Tr, the input of which is connected to the PM tone channel, a PF bandpass filter, the input of which is connected to the output transformer Tr, an amplifier with an adjustable gain UARU, the input of which is connected to the output of the PF bandpass filter, phase detector PD, the first input of which is connected to the amplifier output with adjustable gain UARU, a low-pass filter low-pass filter, the input of which is connected to the output of the phase detector PD, pulse shaper FI, input otorrhea connected to the output of low pass filter LPF, a limiting amplifier RO whose input is connected to the output of the amplifier with adjustable

gain UARU, a programmable logic integrated circuit FPGA, which implements a device for generating a reference voltage UVON, the input of which is connected to the output of the amplifier-limiter UO, and the output is connected to the second input of the phase detector PD, the first state register PrC1, two inputs of which are connected to circuits DATA and RECORDING of the ISA bus, frequency divider D, the two inputs of which are connected respectively to the outputs of the device for generating the voltage reference UVON and the first status register PrG1, clock synchronization circuit and STS, the two inputs of which are connected respectively to the outputs of the pulse shaper FI and the frequency divider D, a data register, two inputs of which are connected respectively to the output of the pulse shaper FI and the first output of the clock synchronization circuit STS, the SCC cyclic synchronization circuit, the two inputs of which are connected respectively the output of the FI pulse shaper and the first output of the STS clock synchronization circuit, and the first output is with the ISA bus IR2 circuit, a dual-port RAM, five inputs of which are connected respectively, with the ADDRESS, READING of the ISA bus circuits, the RGD data register DATA output and the second and third ADDRESS outputs of the SCC cyclic synchronization circuit, and the output with the ISA bus DATA input circuit, the second RgC2 status register, the two inputs of which are connected respectively to the second output of the clock circuit STS synchronization and ISA bus READING circuit, and output with ISA bus input circuit.

The telecode transmitter in T-235-1L codes (wired channel) contains a G generator, a programmable logic integrated circuit FPGA, two inputs of which are connected respectively to the output of the G generator and ISA bus, the first digital-to-analog converter DAC1, the input of which is connected to the first output of the programmable FPGA logic integrated circuit, a second DAC-to-analog converter, two inputs of which are connected respectively to the second output of the FPGA programmable logic integrated circuit and the output of the first digital-to-analog converter DAC1, a modulator FM / BI M, two inputs of which are connected respectively to the output of the second digital-to-analog converter DAC2 and the third output of a programmable logic integrated circuit FPGA, a low-pass filter, an low-pass filter, the input of which is connected to the output of the modulator M, amplifier U, the input of which is connected with the output of the low-pass filter of the low-pass filter, the output transformer Tr, the input of which is connected to the output of the amplifier of the UK, and the output with the channel of the tone frequency of the PM.

The T-235-1L telecode transmitter (radio) contains a PFM galvanic isolation circuit, the input of which is connected to the receiving channel of the radio transmitter

(radio receiver) PCT, the first pulse shaper FI1, the input of which is connected to the output of the PLM galvanic isolation circuit, a programmable logic integrated circuit FPGA, the input of which is connected to the output of the first pulse shaper FI1, the transmission galvanic isolation circuit of the transmission, the input of which is connected to the first output of the programmable logic FPGA integrated circuit, radio control circuit, the input of which is connected to the second output of the programmable logic integrated circuit FPGA, and the output with the control input is glad PCT outliers, the second pulse generator FI2 having an input coupled to an output electrical isolation XMT schema and the output of the transceiver PCT.

The telecode receiver in the T-235-1L codes contains a series-connected output input to the input transformer Tr, a PF bandpass filter, an amplifier limiter UO and a programmable logic integrated circuit FPGA, the input of the input transformer Tr is connected to the communication channel of the Tonal frequency of the PM, and the programmable logic output FPGA integrated circuit with ISA bus.

The controller of the navigation equipment contains the first, second, third and fourth limiters-pulse shapers FI1, FI2, FI3 and FI4, the inputs of which are connected respectively to the outputs + Δx, - Δx, + Δy, - Δy of the navigation equipment, programmable logic integrated circuit FPGA, which implemented the first and second reversible counters PC1 and PC2, two inputs of which are connected respectively to the outputs of the first and second pulse limiters-FI1 and FI2 (along the X coordinate) and with the outputs of the third and fourth limiters pulse generators FI3 and FI4 (along the Y coordinate), the buffer register of the coordinate X РгХ, the two inputs of which are connected respectively to the output of the first reversible counter PC1 and the READING circuit of the ISA bus, the buffer register of the coordinate Y is PgY, the two inputs of which are connected respectively to the output of the second reversible counter PC2 and the ISA bus READ circuit, and the output is with the ISA bus DATA circuit, the first comparison circuit X, the two inputs of which are connected respectively to the output of the first reversible counter PC1 and the DATA output of the buffer register of the X coordinate RxX, and the output one - with the ISA bus IRQ7 circuit, a second comparison circuit Y, the two inputs of which are connected respectively to the output of the second reversible counter PC2 and the output of the Y coordinate coordinate register PgY, and the output - to the ISA bus IRQ7 circuit.

The telecode transmitter (for product 9с520) contains a KG crystal oscillator, a programmable logic integrated circuit FPGA, two inputs of which are connected respectively to the output of a KG crystal oscillator and ISA bus, a PF bandpass filter,

the input of which is connected to the first output of the FPGA programmable logic integrated circuit, the DAC digital-to-analog converter, the two inputs of which are connected respectively to the second output of the FPGA programmable logic integrated circuit and the output of the PF bandpass filter, the OFM modulator, whose two inputs are connected respectively to the third output of the programmable logic FPGA integrated circuit and digital-to-analog converter DAC output, amplifier U, the input of which is connected to the output of the OFM modulator, output transformer p Tp having an input connected to the output of the amplifier, and the output from the communication channel tone PM.

List of figures, drawings and other materials

Figure 1 shows the structural diagram of the MULTIPLEXOR DATA TRANSFER (module BR21-407).

Figure 2 shows the functional diagram of the telecode transmitter ASPD-U.

Figure 3 shows the functional diagram of the telecode receiver ASPD-U.

Figure 4 shows the functional diagram of the telecode transmitter in codes T-235-1 L (wired channel).

Figure 5 shows the functional diagram of the telecode transmitter T-235-1L (radio).

Figure 6 shows the functional diagram of the telecode receiver in codes T-235-1 L.

Figure 7 shows the functional diagram of the controller of navigation equipment.

On Fig is a functional diagram of a telecode transmitter (for product 9s520).

Figure 9 shows the structure of code combinations in the "OK OKK1" mode.

Figure 10 shows the structure of code combinations in the "OK OKK2" mode.

Figure 11 shows the structure of code combinations in the ADF type ASPD-U.

On Fig shows the structure of code combinations in the ADF type 9C520.

An example embodiment of the device

The data transmission multiplexer (Fig. 1) contains an ASPD-U 1 telecode receiver, an ASPD-U 2 telecode transmitter, a T-235-1L 3 telecode receiver, a T-235-1L 4 telecode transmitter, and a TNA- navigation equipment controller 4 5, telecode transmitter (for product 9c520) 6, interrupt controller 7, read / write control circuit 8, telecode transceiver in codes T-235-1L (radio) 9, system bus ISA 10. Figure 1 shows: a communication channel for tone frequency (PM) 11, a bi-pulse communication channel (BI) 12, a phase modulation communication channel 13, a radio channel 14, 15.

The ASPD-U 2 telecode transmitter (FIG. 2) contains a band-pass filter (PF) 17, a digital-to-analog converter (DAC) 18, an amplifier (U) 19, an output transformer (Tr) 20, a programmable logic integrated circuit (FPGA) 21, realizing the register of the amplitude of the output signal (РГА) 22, the state register (РГС) 23, the phase modulator (FM) 24, the frequency divider (Д) 25, the accumulating counter with the decoder (НС) 26, the dual-port random access memory (RAM) 27, the shaper correction signal (FCC) 28, multiplexer 29, as well as a crystal oscillator (G) 30.

The ASPD-U 1 telecode receiver (Fig. 3) contains an input transformer (Tr) 31, a band-pass filter (PF) 32, an amplifier with an adjustable gain (U AGC) 33, a phase detector (PD) 34, a low-pass filter (LPF) 35, a pulse shaper (FI) 36, an amplifier-limiter (UO) 37, and a programmable logic integrated circuit (FPGA) 38 that implements a device for generating a reference voltage (UFON) 39, a frequency divider (D) 40, a clock synchronization circuit (STS) 41 , data register (RGD) 42, cyclic synchronization scheme (SCS) 43, two-port operational memory ayuschee RAM unit 44, a first status register (PC1) 45, a second status register (PC2) 46.

Telecode transmitter (wired channel) 4 (figure 4) contains a quartz-stabilized generator (G) 47, programmable logic integrated circuit (FPGA) 48, the first and second digital-to-analog converter (DAC1) 49 and (DAC2) 50, FM modulator / BI 51, low-pass filter (LPF) 52, amplifier (U) 53, output transformer (Tr) 54.

Telecode transmitter T-235-1L (radio) 9 (Fig. 5) contains a receiver galvanic isolation circuit (PFP) 55, a first pulse shaper (FI1) 56, a programmable logic integrated circuit (FPGA) 57, a galvanic circuit

transmitter isolation (Rx) 58, radio control circuit 59, second pulse shaper (FI2) 60.

Telecode receiver in the codes T-235-1L 3 (Fig.6) contains an input transformer (Tr) 61, a bandpass filter (PF) 62, an amplifier-limiter (UO) 63, a programmable logic integrated circuit (FPGA) 64.

The controller of the navigation equipment 5 (Fig.7), contains the first, second, third and fourth limiters-pulse shapers (FI1) 65, (FI2) 66, (FI3) 67, (FI4) 68, programmable logic integrated circuit (FPGA) 69 which implements the first and second reversible counters (PC1) 70 and (PC2) 73. buffer coordinate registers (PrX) 71 and (PrY) 74, the first and second comparison schemes X 72 and Y 75.

The telecode transmitter (for product 9c520) 6 (Fig. 8) contains a quartz stabilized generator (KG) 76, a programmable logic integrated circuit (FPGA) 77, a bandpass filter (PF) 78, a digital-to-analog converter (DAC) 79, a modulator ( OFM) 80, amplifier (U) 81, output transformer (Tr) 82.

Module purpose

Data transmission multiplexer - the BR21-407 module (hereinafter referred to as the module) is data transmission equipment (APD) operating in the codes of ASPD-U equipment (DEI3.031.000), T-235-1L equipment (LT1.600.012), products 1L110, 1L15 and 9C520, as well as the controller of navigation equipment TNA-4.

The module is designed for simultaneous independent data exchange with ASPD-U equipment (or block C51 DEI2.000.004), T-235-1L equipment, via a radio channel formed by P163-50U radio station and P163-UP radio receiver or via a wired communication channel.

The module is designed to transmit information to the IUTS device 9C520 through a wired communication channel.

The module is designed to provide interaction between computers and TNA-4 equipment.

Module Specifications

Characteristics of the ADF operating in the ASPD-U hardware codes.

The characteristics of the module are shown in table 1.

Table 1 - Characteristics of the ADF ASPD-U Parameter Value Bit depth, bit 40 Baud rates, bps 234,468 Type of modulation OFM Mode of operation Work, Train Codogram structure Codograms of ASPD-U equipment

A communication channel can be formed:

- "Crossbow" type radio facilities at the "AVSK" input (tone frequency channel);

- field telephone cable type P274M (wired channel);

- telephone cable type P269 or PTRK (wired channel). The module provides interfacing with communication channels (channel of tone frequency of KTCH and wired channel of PC) with characteristics:

- value of input and output resistances at points of connection to communication lines:

1) for KTCH - (600 ± 90) Ohm;

2) for PC - (600 ± 90) Ohm,

- the level of output signals at the points of connection to the communication lines for KTCH - minus 3.5 dB;

- the actual value of the output voltages for the PC is 0 dB, (h0.8 V);

- the actual value of the output voltages for the PC at ranges of more than 10 km is 6 dB (h1.55 V); frequency 1873.1475 Hz (hereinafter referred to as 1873 Hz),

- the minimum voltage level at the input of the receiver is minus 30 dB. In the “OFM” mode, the coding is based on modulating a burst of logic “1” with a sinusoidal voltage that is in phase with the phase of the previous burst, of a logic “0” with a sinusoidal phase voltage that is 180 ° different from the phase of the previous burst.

Through a channel of type ASPD-U, the module provides an exchange of TKI through wire channels with a transmission coefficient of at least 0.95 at a maximum range of at least 15 km at a speed of 234 bit / s and 468 bit / s.

Transmission levels for various types of communication channels are shown in table 2

Table 2 - ASPD-U ADF transmission levels Method (type) of reception and transmission The speed of reception and transmission, bit / s Type of communication channel (designation) Canal-forming agents Transmission levels OFM
modulation 234, 468 Tone Channel (KFC) R-163-50U minus 3.5 dB Wired Channel (PC-OFM) Field P274M cable Field P269, P274M or PTRK cable 0 dB, 6 dB minus 3.5 dB

Characteristics of the ADF working in the codes of the T-235-1L equipment.

The characteristics of the ADF working in the codes of the T-235-1L equipment are given in table 3.

Table 3 - the characteristics of the ADF type T-235-1L Parameter Value Note Bit depth, bit 69,117 Baud rates, bps 1200 FM 1200 BI, 2400 BI, 4800 BI Type of modulation World Cup, Bi Operating modes OKODK-1 OK OKK-2 Without the formation of the DRC Error Protection Device Modes UZO-1, UZO-2, UZO-3 Codogram structure Corresponds to the structure of the codograms of the equipment T23 5-1L (LT1.600.012)

A communication channel can be formed:

- "Crossbow" type radio facilities at the "AVSK" input (tone frequency channel);

- radio equipment of the type "Crossbow" at the input of "IMP" (pulse channel);

- field telephone cable type P274M (wired channel);

- telephone cable type P269 or PTRK (wired channel). The module protects information from errors and converts it into a form suitable for transmission by FM and BI methods at the junction C1-PM in accordance with GOST 25.007-81 and at the interface C1-FL in accordance with GOST 27.232-87

The module provides interfacing with communication channels (KTCH, PC and pulse channel IR) with the following characteristics:

- the value of the input and output resistances at the points of connection to the communication lines for KTCH - (600 ± 90) Ohm;

- the level of output signals at points of connection to communication lines for KTCH:

1) minus 28 dB;

2) minus 3.5 dB;

3) 0 dB;

4) 4 dB.

- values of input and output resistances at points of connection to communication lines for PC - (150 ± 90) Ohm,

- the actual value of the output voltages for the PC:

1) 0.025 ± 0.002 V;

2) 0.4 ± 0.1 V;

3) 1 ± 0.1 V;

4) 2 ± 0.1 V.

- the values of the output resistance at the points of connection to the communication lines for IR are not less than 3.6 kOhm, the magnitude of the output voltage range is from 10 to 13 V. The transmission levels for various types of communication channels are given in table 4.

Table 4 - Transmission levels APD T-235-1L Method (type) of reception and transmission The speed of reception and transmission, bit / s Type of communication channel (designation) Canal-forming agents Transmission levels Frequency modulation 1200 Tone Channel (KFC) R-163-50U minus 3.5 dB Wired Channel (PC-FM) Field cable P274M, P269, PTRK Odb Bi-pulse coding 1200, 2400, 4800 Wired Channel (PC-BI) Field P274M cable Field P269 or PTRK cable 1V (2V span) 0.4 (0.8V span) Pulse Channel (IR) R163-50U Logical zero level from minus 0.5 V to 1.5 V Logical unit level from 10 V to 13 V

The minimum level of the receiving signal is:

- for KTCH not less than minus 27 dB;

- for PC-BI not less than 0.025 V.

For KFC, the module provides an error coefficient of not more than 10 ^-4 with a signal-to-noise difference of 11 dB (at the receiver input in FM mode).

In the "FM" mode, the module uses the characteristic frequencies:

- for the symbol "0" - 2100 Hz;

- for the symbol "1" -1300 Hz.

Through a channel of type T235-1L, the module provides an exchange of TKI through wire channels with a transmission coefficient of at least 0.9 at a maximum range of at least 10 km at a speed of 1200 bps, 2400 bps and at least 5 km at a speed of 4800 bps .

In the "BI" mode, the encoding is based on the conversion of sending a logical "1" to a bi-pulse "10" or "01" with a polarity coinciding with the polarity of the previous bi-pulse, and sending a single element "0" of an information signal to a bi-pulse "10" or "01" opposite polarity with respect to the previous bi-pulse.

Characteristics of the ADF working in product codes 9C520.

The characteristics of the ADF working in the product codes 9C520 are shown in table 5.

Table 5 - Characteristics of the ADF working in the product codes 9C520 Parameter Value Note Bit depth, bit 32 Bit rate, bps 300 Type of modulation OFM Link Wired channel via cable type P274M or Special cable from the product 9S520 Codogram structure Corresponds to the structure of codograms of the product 9C520

The module provides pairing with communication channels (PC) with the following characteristics:

- value of output resistance at the points of connection to communication lines - (600 ± 90) Ohm;

- the actual value of the output voltage for the PC is 0 dB.

Computer Interface Characteristics

The module interacts with the CPU through the ISA system bus for interrupts when data is transmitted or received through software-accessible registers.

In this case, the exchange of information occurs byte-by-bit using the least significant bits of the data bus (SD0 - SD7) and the 10-bit address bus (SA0-SAA9).

Interface characteristics with TNA-4 equipment

The module provides pairing with TNA-4 equipment with the following characteristics:

- the amplitude of the pulses along the circuits + X, -X, + Y, -Y - from 22 to 30 V;

- discreteness of increment of coordinates X, Y - 10 m.

Module parameters

The parameters of the power supply voltage of the module are shown in table 6.

Table 6 - Parameters of voltage supply Supply Voltage, V Maximum current consumption, A Nominal value, V Tolerance, In +5 +12 -12 ± 0.25 ± 0.6 ± 0.6 0.12 0.075 0.075

The module in the communication lines with the computer has TTL levels with parameters:

- Ulog "0" no more than 0.4 V;

- Ulog "1" not less than 2.5 V;

The module is ready to work after power-up no more than 3 s (not taking into account the time it takes for the receivers to enter synchronism).

Module composition

The module consists of the following functional devices:

- Telecode data transmitter, operating in hardware codes ASPD-U 2;

- Telecode data receiver, operating in hardware codes ASPD-U 1;

- Telecode data transmitter operating in hardware codes T-235-1L 4;

- Telecode data receiver operating in hardware codes T-235-1L 3;

- Telecode data transmitter operating in the codes of the 9C520 6 module;

- controller of navigation equipment TNA-4 5;

- a node for interfacing a module with the ISA computer system bus (interrupt controller, information writing / reading control circuit) 7, 8;

- Telecode transceiver in the codes T-235-1L (radio) 6.

Design

Structurally, the module is implemented on a single-board design according to the Euromechanics standard, size 6U (260 x 180 x 20 mm).

The output of communication lines between the module and R163-50U, R163-UP and TNA-4 on the strip of external computer connectors are structurally implemented using cables made by the consumer of the module independently.

The module in the computer is installed in the guide frame and is fastened with two captive screws. The module is removed from the computer frame by turning the handles located on the edges of the external side of the module.

On the module strip are placed:

- the PHASE indicator provides an indication of the presence of synchronism of the ASPD-U receiver;

- The INF indicator provides an indication of the availability of T235-1L receiver information;

- X3 connector for connecting the “Crossbow” series of radio equipment;

- X4 connector for connecting navigation equipment TNA-4;

- X5 connector for connecting the T-235-1L channel in FM mode;

- X6 connector used to output the control signals of the module.

Connectors X1 and X2 for communication with the ISA bus and Baget computer power circuits are located on the opposite side of the board relative to the module bracket.

Operating modes

The operating modes of the module are determined programmatically by writing information to the registers of the state of the module CGS and jumpers installed on the module board.

Install jumpers by soldering.

The choice of module parameters is determined by the consumer, depending on the type and configuration of the computer in which the module is planned to be installed.

The base address of the I / O registers, module code, module interrupt vector are set by jumpers on the board.

Operating modes of the ADF type T-235-1L

APD working in the codograms of the T-235-1L equipment provides operating modes:

- "OK ODK1" - independent reception and transmission in the address or circular mode;

- "OK ОДК2" - independent reception and transmission without formation of a CDD codogram.

The module provides transmission and reception of code combinations with a length of 69 or 117 elements with the structure adopted in the T-235-1L equipment.

In the "OK ОДК1" mode, the module provides a transmission mode with the issuance of two code combinations of "points" (a sequence of alternating ones and zeros) and one combination of phase start (KPF) during initial synchronization, as well as one KPF in place of each 96 code combination in the block transmitted data.

In the "OK ОДК2" mode, the module provides a transmission mode with the issuance of two code combinations of "points" and two KPPs (inverse and direct) at the initial synchronization, as well as two KPPs (inverse and direct) in place of each 96 and 97 code combinations in the block transmitted data.

The module provides the issuance of "Silence" code combinations to the communication channel in the case when no information was received from the computer by the time the transmission of the next codogram began.

In all modes, the computer generates, transmits to the module, and receives from it the first 53 or 101 bits of code combinations. Thus, the signs of a circular or address message are generated by the computer.

After the information from the computer is stopped, the module for maintaining connection with subscribers transmits the "Silence" code combinations.

When receiving “Silence” code combinations, the module blocks their issuance to the computer.

The structure of the code combinations used in the "OK ODK1" mode is shown in Fig.9.

The values of the service unit items are shown in table 7.

Table 7 - the value of the service unit items Service unit of a code combination Type of message M FROM 1st category 2nd category 3rd category 4th category X X X X 1 Address 1 0 X X 0 Circular 1 1 X X about Silence Note - The sign "X" is an arbitrary value of a given unit element (0 or 1).

In the "OK OKK2" mode, the module provides simultaneous transmission and reception of code combinations with the structure shown in Fig. 10.

Thus, all 53 or 101 bits of the code combination are informational, with 1 bit being the oldest in weight.

In the absence of information from the computer (that is, at the beginning of the transmission of the next codogram to the computer channel, it did not write data to the module), the module transmits "Silence" code combinations to maintain connection with subscribers.

Operating modes of the ADF type ASPD-U The APD operating in the ASPD-U codograms provides the operating modes:

- "Rare";

- “Frequent”;

- "Plume".

In the “Rare” mode, information is exchanged with 40-bit codograms at a speed of 234 bit / s.

In the "Frequent" mode, information is exchanged with 40-bit codograms at a speed of 468 bit / s.

In the "Loop" mode, the input of the receiver is connected to the output of the transmitter of the module for conducting an autonomous check.

The structure of the codograms in the ADF type ASPD-U is shown in Fig.11.

In the absence of information from the computer (that is, at the beginning of the transmission of the next codogram to the computer channel, it did not write data to the module), the module transmits code combinations consisting of "0" in the information part to maintain a connection with subscribers.

Operating modes of the ADF type 9S520

The transmitter operating in the product codes 1L110, 9C520 provides transmission with 32-bit code codes at a speed of 300 bit / s.

The structure of the codograms in the ADC of type 9C520 is shown in Fig. 12.

In the absence of information from the computer (that is, at the beginning of the transmission of the next codogram to the computer channel, it did not write data to the module), the module transmits a code combination consisting of "0" in the information part and synchronizing bits to maintain connection with subscribers.

Functional nodes and their purpose

The module is based on the principles of signal generation for simultaneous and independent data transmission through three transmitting channels and simultaneous independent reception on two receiving channels in order to ensure the exchange of telecode information between subscribers of a mobile communication system both by radio (KTCH or IR), and by wire communication lines.

The block diagram of the module is presented in figure 1.

The module includes the following functional units:

- Telecode data transmitter operating in the hardware codes ASPD-U (PRD1) 2;

- Telecode data receiver, operating in hardware codes ASPD-U (PRM1) 1;

- Telecode data transmitter operating in hardware codes T-235-1L (PRD2) 4;

- Telecode data receiver operating in hardware codes T-235-1L (PRM2) 3;

- Telecode data transmitter working in codes of module 9С520 (PRDZ) 6;

- controller of navigation equipment TNA-4 5;

- a node for interfacing a module with the ISA computer system bus (interrupt controller, information writing / reading control circuit) 7, 8;

- Telecode transceiver in codes T-235-1L (radio) 9.

Digital transmitters PRD1 2, PRD2 4, PRDZ 6 are intended for storing eight-bit information words received from RAM (number of words from 4 to 16) when recording and transmitting to the communication channel in the form of telecode information codograms of 69,117.40, or 32 elements .

Digital receivers PRM1 1, PRM2 3 are designed to analyze the received information from the communication channel and transmit it through RAM and then through the ISA bus to the computer during the read operation.

The TNA-4 hardware controller is designed to receive X, Y rectangular coordinates increments from the TNA-4 hardware, store them temporarily, and output these values through the ISA system bus to the computer.

The unit for interfacing the module with the ISA computer bus 7, 8 provides synchronization of the exchange of information between data registers and the status of transceivers and computers.

Assignment of control and indication modules

The operation of the module is controlled programmatically by recording information about operating modes in the device status registers.

Indication elements are placed on the front panel of the module:

- the PHASE indicator provides an indication of the presence of synchronism of the ASPD-U receiver;

- INF indicator - provides an indication of the availability of information of the T235-1L receiver.

The interaction of the module with the computer processor.

The module interacts with the central processor (CPU) through the ISA system bus for interrupts when the transmission or reception of information through program-accessible I / O registers is ready. In this case, the exchange of information occurs byte-by-bit using the lower bits of the data bus (SDO - SD7) and the 10-bit address bus (SA0-SAA9).

Organization of information interface

Information reception and transmission, as well as the operation mode of the ADF, are controlled by computer CPU programs by accessing software-accessible registers.

The organization of data exchange is carried out by the interrupt received by the CPU from the module.

The type of interrupt request is determined through the interrupt register Prg.

The description of the fields of the Prg register is presented in table 8.

Table 8 - Description of the fields of the register Prg Register designation Discharge number Field designation Field content Prg 7..4r KM module code, set by jumpers on the module board 3p Reserve 2p 3PR Ust2 2 digit device number code 1p 3PR Ust1 1 digit device number code 0p 3PR Ust0 0 digit device number code

The device number code in the interrupt register corresponds to the number (code) of the status register of this device.

Interruption of each device can be blocked by setting to “0” the corresponding category of the mask register (PrMask).

Description of the fields of the RgMaski register is presented in table 9.

Table 9 - Description of the fields of the register RgMaski 7p 6p 5p 4p 3p 2p 1p 0p Mask 7 Mask 6 Mask 5 Mask 4 Mask 3 Mask 2 Mask 1 Mask 0 TNA-4 Reserve PRD 9S520 PRD ASPD-U PFP ASPD-U PRD-235 PRM-235 Reserve

The synchronization of the processes of receiving and transmitting data is carried out using the interrupt signal received by the computer from the module when it is ready to transmit information to the computer or receive information from the computer.

Having received the interrupt signal, the computer processor, under the control of the interrupt processing program, must read the interrupt register Prg module. The fact that the processor reads the interrupt register indicates the reception of this interrupt and the possibility of generating an interrupt from the next device in the module.

The time from the moment of generation of the interrupt signal to the moment of reading the interrupt register is calculated by the formula:

T _ThrRgPr ≤ N / V / K, (1)

where N is the number of bits in the codogram of a device operating at maximum frequency;

V is the speed of data reception / transmission of a device operating at maximum frequency;

K is the number of devices that simultaneously set an interrupt.

Example: During the operation of all devices of the module and the simultaneous generation of an interrupt request at N = 69, V = 4800, K = 6 ThtRgPr = 69/4800/6 = 2,395822 ms.

Based on the contents of the PrgPr register, the CPU determines the module code and the number (type) of the device that set the interrupt, and then reads (or writes) the data registers of the PrgD and the status register of the PrgS device.

The sequence of accesses to the registers of the RGD of a particular device can be arbitrary.

The reference to the CGS of a specific device should be the last of a series of calls to the registers of the CGD of this device and indicates the completion of the interaction of the CPU with this device.

The frequency of interruption from devices operating to receive / transmit information depends on the speed of reception / transmission and is calculated by the formula:

F = 1 / Tint, (2)

where F is the frequency of formation of the interrupt signal;

Tint - the time interval for receiving / transmitting one CDG through communication channels.

Tint = H / V (3)

where N is the number of bits in the codogram;

V is the speed of data reception / transmission.

The maximum permissible read / write time of the data array for one codogram is calculated by the formula:

T _{Th / W} = (N-1) / V (4)

From the TNA-4 controller, interruption occurs when the coordinate increment code X or Y changes. The period of generation of the interrupt signal from TNA-4 is calculated by the formula:

T _PrTNA = Vob./ Δx, y, (5)

where Voб is the maximum speed of the object;

Δx, Δy - discrete increment of the coordinates X, Y (for TNA-4 Δx, Δy = 10m).

Management of the operating mode and determination of the status of the device is carried out through the status register of the device CGC.

Description and operation of module components

General information

The module performs the functions of transmitting and receiving discrete information by radio means P163-50U and P163-UP in the code of the ASPD-U, T235-1L equipment and provides the issuance of information to the Baget series computers received from the communication channel and TNA-4 equipment.

Switching of operating modes is done programmatically.

Information exchange between the module and the computer is carried out in program mode by means of an interrupt set from the side of the module in the computer.

ASPD-U Telecode Transmitter Node Operation

Functional diagram of the telecode transmitter ASPD-U is shown in Fig.2.

The ASPD-U television transmitter consists of functional devices:

- quartz stabilized generator - G 30;

- frequency divider - D 25;

- accumulating counter with decoder - НС 26;

- two-port random access memory - RAM 27;

- shaper correction signal - FKS 28;

- data multiplexer - MUX 29;

- band-pass filter - PF 17;

- status register - РГС 23;

- register of the amplitude of the output signal - RgA 22;

- digital-to-analog converter - DAC 18;

- phase modulator - FM 24;

- amplifier - U 19;

- output transformer Tr 20.

The output transformer Tr (T2) is connected to the amplifier Y by the primary winding, and by the secondary to the output connector X3 (pins 1,2).

Frequency divider - D, accumulating counter with decoder - NS, dual-port random access memory - RAM, correction signal generator - FCC, data multiplexer - MUX, status register - РГС, register of output signal amplitude - РгА, phase modulator - ФМ are assembled on FPGA chip .

Frequency-stabilized pulses from a quartz oscillator G are fed to a frequency divider D, which, depending on the value of the code coming from the control register of the RGU operating mode, generates the frequencies of the reference carrier oscillation and clock pulses.

The rectangular pulses of the reference carrier oscillation are fed to the PF bandpass filter, which distinguishes the first harmonic of the reference carrier frequency.

Depending on the characteristics and type of channel-forming communication equipment, the amplitude of the reference carrier oscillation is changed using a digital-to-analog DAC multiplier, in which the analog reference carrier oscillation is multiplied by a binary amplitude coefficient coming from the amplitude register PrA.

Clock pulses with a frequency of the corresponding data transfer rate in the telecode channel from the frequency divider D are fed to the accumulating counter with the NS decoder.

In the process of counting clock pulses at the moment the transmitter is ready to receive the next block of data for transmission, an interrupt signal IR1 is generated at the output of the NS decoder, which is transmitted to the CPR interrupt controller.

The interrupt controller analyzes the presence and levels of interruptions that have arrived at a given time and sets the processor interrupt signal on the system bus.

The processor, having received the interrupt, reads the interrupt code from the interrupt controller, which determines the type of device that set the interrupt.

Having determined the type of device, the processor generates a data block for delivery to the communication channel. After that, the processor sets the address code of the dual-port RAM and the next word from the data block on the address bus. The most significant bits of the address go to the address selector CA of the control device, and the lower four bits determine the cell address of the dual-port RAM. In the CA address selector of the control device, the incoming address is compared with the base address of the device. In the case of a match, a signal is issued that allows the next word in the data block to be written to dual-port RAM.

By the time the next data block is transferred to the communication channel, they are in the first two port RAM. At the same time, the counter with the NS decoder sets up the address of the word and bit of the data block, respectively, on the dual-port RAM and the MUX data multiplexer. In this case, the next word is read from the dual-port RAM and, using the MUX data multiplexer, is converted into a serial code. Also, under the control of the counter with the NS decoder, after the last bit of the data block has been transmitted, the code combination of the correction signal coming from the FCC correction signal generator is added to the data stream to mark the end of the data block. At the same time, a codogram of one data block is formed at the output of the MUX data multiplexer.

For transmission to the channel of the tonal frequency, the sequence of binary data bits is converted into a sine wave with relative phase modulation.

Modulation takes place in the phase modulator FM, on one input of which the amplitude code from the amplitude register is received, and on the other input is a sequence of binary data from the MUX data multiplexer.

Under the influence of binary data bits in the phase modulator FM, the phase changes in the amplitude code and thereby forms the code of the output phase-modulated signal.

The code of the amplitude of the output signal is phase-modulated in accordance with the information supplied to the multiplying digital-to-analog converter of the DAC, the analog input of which receives the carrier sinusoidal oscillation from the output of the bandpass filter. At the output of the DAC, a sinusoidal phase-modulated oscillation in amplitude is proportional to the amplitude code.

From the output of the DAC, the signal enters the amplifier U and then through the output transformer Tr enters the channel-forming equipment, which can be a radio station or a wired communication channel.

ASPD-U Telecode Receiver Assembly Operation

Functional diagram of the telecode receiver ASPD-U is shown in Fig.3.

The ASPD-U television receiver consists of functional devices:

- input transformer Tr 31;

- band-pass filter - PF 32;

- phase detector - FD 34;

- low-pass filter - low-pass filter 35;

- pulse shaper - FI 36;

- amplifier with adjustable gain - UARU 33;

- amplifier-limiter - UO 37;

- a device for the formation of a reference voltage - U FON 39;

- frequency divider - D 40;

- clock synchronization scheme - STS 41;

- cyclic synchronization scheme - SCS 43;

- data register - РГД 42;

- two-port random access memory - RAM 44;

- status register - РгС1 45 and РгС 2 46.

The input transformer Tr (T1) is connected by the primary winding to the input connector X3 (pins 9.10), and by the secondary winding to the automatic gain control circuit of the AGC.

The device for generating the reference voltage is UFON, the frequency divider is D, the clock synchronization circuit is STS, the cyclic synchronization circuit is STS, the data register is RGD, the dual-port random access memory device is RAM, the status register is RGS assembled on the FPGA chip.

The phase-modulated signal from the communication channel through the input transformer Tr enters the automatic gain control unit of the UARU, in which the amplitude of the input signal is stabilized. The stabilized input signal is fed to the amplifier-limiter UO, from the output of which a digital signal is formed with levels of TTL logic. A carrier frequency is extracted from a digital input signal using a UVON reference voltage isolation device, which coincides in phase with the phase of the carrier frequency of the input information.

The reference frequency is fed to the PD phase detector, the second input of which receives an input signal stabilized in amplitude. Since the phase of the input signal changes synchronously with the transmitted information, and the phase of the reference voltage is synchronous and in phase with the carrier frequency, the envelope of the input signal corresponding to the received information is allocated at the output of the PD phase detector.

The reference frequency is also supplied to the frequency divider D, which, depending on the operating mode under the control of the state register РГС, generates a frequency of clock signals equal to the information transfer speed.

The envelope signal of the input signal is filtered by the low-pass filter of the low-pass filter from the carrier frequency and interference, and using the pulse shaper the FI is converted into an information digital signal with TTL logic levels.

In the information digital signal obtained in this way, the characteristic recovery times constantly fluctuate. This occurs as a result of amplitude-frequency, phase-frequency distortions in the communication channel, as well as under the influence of interference present in the communication channel.

To eliminate fluctuations, information is recorded by the gating method. In this case, the STS clock synchronization unit generates a gating signal, which coincides with the middle of a single transmission of an information signal. This signal records information in the data register RGD.

To determine the start time of the codogram, an informational digital signal is fed to the cyclic synchronization unit of the SCC, which extracts information from the correction signal from the general information stream and fixes its arrival time. As a result, the word address counter and the input information bit in the cyclic synchronization unit of the SCS works in phase with the corresponding counter on the transmitting side.

The SCS cyclic synchronization unit generates the word address of the information block and the pulse of recording information in the DPRA dual-port random access memory. After recording the entire data block, the SCC cyclic synchronization node generates an IR2 interrupt signal, which is transmitted to the CPR interrupt controller.

The computer processor, under the control of the television receiver interruption processing program, reads the information of the data block from the dual-port random access memory RAM and from the status register of the receiver CGC, which stores the current state of the cyclic synchronization unit and information about the mode of operation of the television receiver.

The operation of the telecode transmitter unit in the codes of the T-235-1L equipment

The functional diagram of the telecode transmitter when working on a wired channel for FM and BI modulations and on the radio channel for FM modulation is shown in Fig. 4.

The television transmitter when working on a wired channel in the codes T-235-1L consists of functional devices:

- quartz stabilized generator - G 47;

- digital-to-analog converter - DAC1 49, DAC2 50;

- FM / BI modulator - M 50;

- low-pass filter - low-pass filter 52;

- amplifier - U 53;

- output transformer Tr 54.

The output transformer Tr (T5) is connected to the amplifier Y by the primary winding, and by the secondary winding to the output connector X5 (pins 1,2).

The functional diagram of the telecode transceiver when working on the radio channel with BI modulation is shown in Fig.5.

A telecode transceiver when operating on a radio channel with BI modulation consists of functional devices:

A television transmitter in the T-235-1L codes consists of functional devices:

- galvanic isolation circuit PRM 55;

- galvanic isolation circuit PRD 58;

- pulse shapers - FI 56, 60;

- radio control circuits 59.

The information processing device is assembled on an FPGA chip.

The operation of the telecode receiver unit in the hardware codes T-235-1L

The functional diagram of the telecode receiver when working on a wired channel is shown in Fig.6.

A television receiver when working on a wired channel consists of functional devices:

- input transformer Tr 61;

- band-pass filter - PF 62;

- amplifier-limiter - UO 63;

- information processing device - FPGA 64.

The input transformer Tr (T4 is connected to the input connector X5 (contacts 3.4) by the primary winding and to the band-pass filter by the secondary winding. The information processing device is assembled on an FPGA chip.

The operation of the controller of navigation equipment TNA-4 Functional diagram of the controller of navigation equipment is shown in Fig.7.

The controller of navigation equipment consists of functional devices:

- pulse limiters-FI1 65, FI2 66, FI3 667, FI4 68;

- reverse counters PC1 70, PC2 73;

- buffer registers of coordinates РГХ 71, РгY 74;

- comparison schemes X, Y 72, 75.

Reversible counters PC1, PC2, buffer registers of coordinates РГХ, РгY, comparison schemes X, Y are assembled on a FPGA chip (D5).

During the movement of the object from the navigation equipment TNA-4-6, impulses of the coordinate increment “+ ΔX”, “-ΔX”, “+ ΔY”, “-ΔY” are received. The number and sequence of pulses arrives depends on the course of the object. The increment pulses of the coordinates are supplied to the pulse limiters-FI1, FI2, FI3, FI4 for normalization in amplitude in accordance with the levels of TTL logic signals.

The generated impulses of the increment of coordinates "+ ΔX", "-ΔX", "+ ΔY", "-ΔY" are counted by reversible counters PC1, PC2. The value of the increment of the counters is written into the buffer registers of coordinates PgX, PgY.

Upon receipt of the next impulses of the increment of coordinates “+ ΔX”, “-ΔX”, “+ ΔY”, “-ΔY”, the values of the current increments from the coordinate registers PrX, PrY are compared in the comparison schemes with the updated increments of coordinates in the reversible counters PC1, PC2.

If the increment values differ, which indicates the arrival of the next increment pulse, the comparison circuit generates an IRQ 7 processor interrupt request pulse. When an interrupt request is received, the processor reads the increment values of the RAM coordinates through the data bus.

The operation of the telecode transmitter unit in the hardware codes 9C520

The functional diagram of the telecode transmitter when working on a wired channel with FM and BI modulations and on a radio channel with FM modulation is shown in Fig. 8.

The transmitter when working on a wired channel in codes 9C520 consists of functional devices:

- quartz stabilized generator - G 76;

- information processing device - FPGA 77;

- digital-to-analog converter - DAC 79;

- band-pass filter - PF 78;

- modulator - OFM 80;

- amplifier - U 81;

- output transformer Tr 82.

The output transformer Tr 82 the primary winding is connected to the amplifier U, and the secondary to the output connector X3

Industrial applicability

This technical solution is industrially feasible, has the necessary functionality for transmitting data via wired and radio communication channels when working in special equipment algorithms, provides pairing with navigation equipment, has a compact embodiment and low power consumption.

Claims (8)

1. A data transfer multiplexer containing the ISA system bus of a specialized electronic computer, an interrupt controller connected to the IRQ1 - IRQ7 interrupt circuits from the device blocks and the IRQ output and data I / O to the ISA system bus, a read / write control circuit connected at the output by the READ and WRITE circuits with the device blocks, at the DATA, ADDRESS I / O and inputs W and R with the ISA system bus, characterized in that it additionally contains the DATA telecode connected to the ISA system bus new ASPD-U receiver, ASPD-U telecode transmitter, T-235-1L telecode receiver, T-235-1L telecode transmitter, telecode transmitter (for 9s520 product), TNA-4 interface with tank navigation equipment, moreover, the channel part telecode receivers and transmitters are connected to the communication channel, as well as a telecode receiver and transmitter in the codes T-235-1L (radio), connected at the input, output and control with a radio station R-163-50U and a radio receiver R-163-UP. 2. The multiplexer according to claim 1, characterized in that the ASPD-U telecode transmitter comprises a crystal oscillator G, a PF bandpass filter, a DAC digital-to-analog converter, the first input of which is connected to an output of a PF band-pass filter, an amplifier U whose input is connected to the output of a digital-to-analog converter DAC, the output transformer Tr, the input of which is connected to the output of the amplifier U, and the output is connected to the channel of the tone frequency of the PM, a programmable logic integrated circuit FPGA, which implements the amplitude register of the output signal PrA and RgC status register, the inputs of which are connected to the ISA bus DATA and RECORD circuits, the FM phase modulator, the first input of which is connected to the output of the amplitude register of the output signal RgA, and the output with the second input of the DAC digital-to-analog converter, frequency divider D, two inputs of which are connected respectively to the output of the state register РГС and the output of the crystal oscillator G, and the first output - with the input of the bandpass filter PF, the accumulating counter - with the decoder NS, the input of which is connected to the second output of the frequency divider D, and the first output - with the ISA bus IR1 circuit, a two-port RAM memory, the first input of which is connected to the second output of the accumulating counter with the NS decoder, and the second, third, fourth and fifth inputs - with the READ, DATA, WRITE, ISA bus ADDRESS circuits, the corrector for correction FCC signal, the input of which is connected to the output of the accumulating counter with the NS decoder, a multiplexer, the three inputs of which are connected respectively to the DATA output of the dual-port random access memory RAM, the output of the correction driver FCC signal and the second output of the accumulating counter with NA decoder, and an output - to a second input of the phase modulator PM. 3. The multiplexer according to claim 1, characterized in that the ASPD-U telecode receiver contains an input transformer Tr, the input of which is connected to the PM tone channel, a PF bandpass filter, the input of which is connected to the output of the input transformer Tr, an amplifier with an adjustable gain UARU the input of which is connected to the output of the band-pass filter PF, a phase detector PD, the first input of which is connected to the output of an amplifier with an adjustable gain UARU, a low-pass filter of the low-pass filter, the input of which is connected to the output of the phase det PD, pulse shaper FI, the input of which is connected to the output of the low-pass filter of the low-pass filter, the amplifier-limiter UO, the input of which is connected to the output of the amplifier with adjustable gain UARU, a programmable logic integrated circuit FPGA, which implements the device for generating the reference voltage UVON, input which is connected to the output of the amplifier-limiter UO, and the output to the second input of the phase detector PD, the first state register PrC1, two inputs of which are connected to the DATA and RECORDING circuits of the ISA bus, d frequency D amplifier, two inputs of which are connected respectively to the outputs of the UVON reference voltage generating device and the first state register РГС1, STS clock synchronization circuit, two inputs of which are connected respectively to the outputs of the pulse shaper FI and frequency divider D, data register, two inputs of which are connected respectively with the output of the FI pulse shaper and the first output of the STS clock synchronization circuit, an SCS cyclic synchronization circuit, the two inputs of which are connected respectively to the output of the generators pulse generator FI and the first output of the STS clock synchronization circuit, and the first output is with the IRA circuit of the ISA bus, a dual-port RAM memory, the five inputs of which are connected respectively to the ADDRESS, READ ISA bus circuits, the DATA output of the data register RGD and the second and third ADDRESS the outputs of the SCC cyclic synchronization circuit, and the output with the ISA DATA bus input circuit, the second state register РсС2, the two inputs of which are connected respectively to the second output of the STS clock synchronization circuit and the ISA bus READING circuit, and the output is from the input circuit Drink ISA bus. 4. The multiplexer according to claim 1, characterized in that the telecode transmitter in T-235-1L codes (wired channel) contains a generator G, a programmable logic integrated circuit FPGA, the two inputs of which are connected respectively to the output of the generator G and the ISA bus, the first digital-to-analog converter DAC1, the input of which is connected to the first output of the programmable logic integrated circuit FPGA, the second digital-to-analog converter DAC2, two inputs of which are connected respectively to the second output of the programmable logic integrated circuit FPGA and the output of the first digital-to-analog converter DAC1, an FM / BI M modulator, two inputs of which are connected respectively to the output of the second digital-to-analog converter DAC2 and the third output of a programmable logic integrated circuit FPGA, a low-pass filter with an LPF whose input is connected to the output of the modulator M, amplifier U, whose input is connected to the output of the low-pass filter of the low-pass filter, the output transformer Tr, the input of which is connected to the output of the amplifier of the UK, and the output to the channel of the tone frequency of the PM. 5. The multiplexer according to claim 1, characterized in that the T-235-1L telecode transmitter (radio) contains a PFM galvanic isolation circuit, the input of which is connected to the receiving channel of the PCT radio transmitter (radio), the first pulse shaper FI1, the input of which is connected to the output of the PFD galvanic isolation circuit, the FPGA programmable logic integrated circuit whose input is connected to the output of the first pulse shaper FI1, the PFD galvanic isolation circuit, the input of which is connected to the first output of the programmable logic FPGA integrated circuit, the radio control circuit, the input of which is connected to the second output of the FPGA programmable logic integrated circuit, and the output with the control input of the PCT radio station, the second pulse shaper FI2, the input of which is connected to the output of the PRD galvanic isolation circuit, and the output to the PCT radio station . 6. The multiplexer according to claim 1, characterized in that the telecode receiver in T-235-1L codes contains a series input output transformer Tr, a PF bandpass filter, a UO limiter amplifier and a FPGA programmable logic integrated circuit, input transformer Tr connected to the communication channel of the tone frequency of the PM, and the output of the programmable logic integrated circuit FPGA with ISA bus. 7. The multiplexer according to claim 1, characterized in that the controller of the navigation equipment contains the first, second, third and fourth pulse-limiters-FI1, FI2, FI3 and FI4, the inputs of which are connected respectively to the outputs + Δx, -Δx, + Δy, -Δu navigation equipment, programmable logic integrated circuit FPGA, which implements the first and second reversible counters PC1 and PC2, two inputs of which are connected respectively to the outputs of the first and second limiters-pulse shapers FI1 and FI2 (along the X coordinate) and output the third and fourth pulse limiters-FI3 and FI4 (along the Y coordinate), the buffer register of the coordinate X РгХ, the two inputs of which are connected respectively to the output of the first reversible counter PC1 and the READING circuit of the ISA bus, the buffer register of the coordinate Y РгY, the two inputs of which are connected respectively, with the output of the second reversible counter PC2 and the READ ISA bus circuit, and the output with the ISA bus DATA circuit, the first comparison circuit X, the two inputs of which are connected respectively to the output of the first reversible counter PC1 and the DATA output of the buffer register of the coordinate X РгХ, and the output is with the IRA7 circuit of the ISA bus, the second comparison circuit is Y, the two inputs of which are connected respectively to the output of the second reversible counter PC2 and the output of the buffer register of the coordinate Y PgY, and the output is connected to the IRQ7 circuit of the ISA bus. 8. The multiplexer according to claim 1, characterized in that the telecode transmitter (for product 9c520) contains a KG crystal oscillator, a programmable logic integrated circuit FPGA, two inputs of which are connected respectively to the output of a KG crystal oscillator and ISA bus, a PF bandpass filter, the input of which connected to the first output of the FPGA programmable logic integrated circuit, a digital-to-analog DAC converter, the two inputs of which are connected respectively to the second output of the FPGA programmable logic integrated circuit and the polo output PF filter, OFM modulator, two inputs of which are connected respectively to the third output of the FPGA programmable logic integrated circuit and the output of the DAC digital-to-analog converter, amplifier U, whose input is connected to the output of the OFM modulator, output transformer Tr, whose input is connected to the amplifier output, and the output with the communication channel of the tone frequency of the PM.