GB1588184A - System for linking data transmitting and receiving devices - Google Patents

Description

(54) SYSTEM FOR LINKING DATA TRANSMITTING AND RECEIVING DEVICES (71) We, HEWLETT-PACKARD FRANCE S.A. a French Company of 5 Avenue Raymond Chanas, F38320 Eybens, France, do hereby declare the invention for which we pray that a patent may be granted to us and the method by which it is to be performed, to be particularly described in and by the following statement: The present invention is related to a system for linking data transmitting and receiving devices.

A plurality of data link systems is known in the art. One example is the "IEEE Standard Digital Interface for Programmable Instrumentation "(IEEE Std 488-1975) published April 4, 1975 by the Institute of Electrical and Electronics Engineers, New York. This standard comprises a byte-serial bit-parallel means to transfer digital data among a group of instruments and system components. It is optimized as an interdevice interface for system components in relatively close proximity able to communicate over a contiguous party-line bus system. The disadvantage of this standard is, that due to the delay times involved it cannot be used for data links over a distance of say some km which may be required for interconnecting data receiving and transmitting stations at different places within a factory.

Another data link system is described in an article "CAMAC: a modular standard", IEEE SPECTRUM April 1976 pp. 50 - 55. This link system is capable of interconnecting up to 62 places via a'serial data transmitting line. However, this serial data transmission is rather complex, since a clock and the addresses for selecting particular stations must be transmitted together with the data. In a serial transmitting system this requires an additional transmission path leading to higher interconnection costs.

According to the present invention there is provided a system for linking data transmitting and receiving devices, comprising: a single channel formed by a serial data transmission line arrangement for interconnecting all devices involved; a controller connected to said line arrangement and being capable of communicating therewith during successive time multiplex polling cycles each polling cycle starting with a synchronizing message from the controller followed by a plurality of communication time windows; and a plurality of stations connected in parallel across said line arrangement and being capable of independently communicating with said controller via said line arrangement during selected time windows, the single channel formed by the line arrangement permitting communication in both directions between each station and the controller, each station comprising addressing means including an internal address counter and a gating means. said address counter being capable of counting to a preselected value in response to every received synchronizing message from said controller and of opening said gating means for the duration of one time window each time after having reached said value, said gating means allowing communication between said station and the controller during said one time window, and the preselected value of the address counter in each station being such that the time window of each station is substantially synchronous with a different one of the communication time windows of the controller's polling cycle, the controller and the stations thereby interfacing the data transmitting and receiving devices with the link system.

According to a preferred embodiment of the invention additional synchronizing signals are transmitted-during each time window from the controller to the station and/or vice versa, respectively, in connection with transmitted data, for exactly synchronizing the data receiving station to the data transmitting controller and/or vice versa, respectively, irrespective of the delay times due to the length of the line arrangement.

Preferably, acknowledgement messages are transmitted upon received data from the station to the controller or vice versa, said acknowledgement messages consisting of bit patterns which are recognizable, irrespective of the delay times due the length of the line arrangement. The arrangement may be such that each station is enabled for communication with the controller only upon an initial synchronizing signal at the beginning of each time window associated to said station.

Thus, according to the invention an addressing scheme for data transmitting and receiving devices is provided which avoids transmitting of addresses via the transmission line arrangement. Addressing is done by the stations themselves upon a single synchronisation message which is sent to all stations simultaneously. The system is very simple on the one hand but, on the other hand, has a good immunity against transmission errors, radio frequency interference and other faults. Each type of mutual communication is possible between stations and controller. In order to detect transmission errors easily, an error detecting code of a commonly known type may be transmitted together with the transmitted data bits.

For improving the probability of correct transmission each bit received by the station and/or controller may be sampled a plurality of times and the majority of either one or zero samples is used to decide whether said bit is a one or a zero.

A predetermined number of successive similar samples may be used to decide in the case of particularly important bits.

An arrangement embodying the invention will now be described by way of example with reference to the accompanying drawings, in which: Figure 1 is a schematic diagram showing a controller and terminals connected thereto via a data link system according to the invention Figure 2 is a time sequence diagram of one polling cycle implemented in the system according to the invention; Figure 3 is the bit pattern of one time window frame when the controller transmits one character to a selected terminal; Figure 4 is the bit pattern of one time window frame when a selected terminal transmits one character to the controller; Figure 5 is a flow chart illustrating the operation of the controller according to Figure 1; and Figure 6 is a flow chart illustrating the operation of each terminal according to Figure 1.

Referring now to Figure 1 there is shown an interconnection cable 11 which may be a simple shielded twisted pair cable with a characteristic impedance of about 100 Ohms at a transmission rate of 25 kbits per second. Cable 11 is terminated by resistors 13 and 15 each having.a resistors 13 and 15 each having a resistance equal to the characteristic impedance of the cable (100 Ohms) in order to avoid reflexions. The maximum length of cable 11 is 4 km in this example. Up to 64 identical connections boxes 171 . . 17N can be connected to cable 11 at any desired point. Plug-in connectors 19 . . . 19N may be plugged into connector boxes 17 . . . 17N for making ohmic contact between cable 11 and connector cables 21, .

21N leading to terminals 231 .23P I,23P+I . . . 23N and to a controller 25. Terminals and controller are described below in more detail. Controller 25 can be connected to cable 11 at any desired point (connector box 17P in this example), provided its distance to each end of cable 11 is not longer than 2 km. It can be seen that up to 63 terminals can be connected to cable 11 and can be controlled by controller 25. Data transmission is possible from controller to terminals and vice versa. Connector boxes 171 . . 17N and plug-in connectors 19. . 9N are simple devices being commonly available.Terminals 231. . .23P 23+ 23N and controller 25 may be connected to other system components via any known interface 27 . 27N, e.g. the above mentioned standard interface IEEE std 488 - 1975.

The addressing and communicating scheme between controller and terminals is now described with reference to Figure 2 showing the time sequence diagram of one polling cycle during which one character can be sent from the controller to each terminal or vice versa. The polling cycle starts with a synchronizing message consisting of a leading one followed by 32 zeros. For the purpose of error free detection the number of subsequent zeros in the synchronizing message is longer than any possible zero-sequence in anyone of the following window frames which are each 28 bits long. The synchronizing message when sent out by controller 25 resets and starts an address counter in each terminal which opens that terminal during a time window for either transmitting or receiving one character. The time delay between synchronizing message and opening of the respective window can be preselected by pre-setting each address counter onto a fixed value. The time windows themselves have a fixed length of 27 bits each. In practice presetting is down in such a manner that the time window of each terminal is synchronous to a different one of the window frames l through M in Figure 2. Window frame 0 is not assigned to any terminal since its leading 'l is still part of the synchronizing message. Since each terminal is associated with a different window frame of the polling cycle, no address message need be transmitted from the controller to the terminals. The address of each terminal is selected only one time after installation by preselecting the address counter of that terminal via an external switching means.It should be noted that this address have nothing to do with the physical location of the terminal along cable 11, i.e. the time sequence of window frames 1 through N-1 need not correspond to the physical sequence of the terminals along cable 11.

The length of the polling cycle according to Figure 2 depends on the number of terminals connected to cable 11, i.e. if 20 terminals are connected, the number of window frames in each polling cycle is M = 20. Referring now to Figures 3 and 4 there are shown the bit patterns formats during one window frame when transmitting data from controller to terminals and vice versa, respectively.

When the controller is in output mode, bits of information are serially shifted according to the controller clock rate. The transmission delay (of the order of 19 lls for the furthest terminal) is allowed for. However, when the controller goes into input mode it will listen to messages that can be as much as one bit late. To account for any delay the controller, when listening to a terminal, will temporarily go into asynchronous mode waiting for a start bit to synchronize its receiving station. Meanwhile, its main clock keeps the original time. This allows the next message to remain synchronous with the beginning of the cycle, and therefore eliminates the need to send an address for the next terminal. Each interchange, whether in input or output mode, includes one such direction change, since each character must be acknowledged by the receiving unit.

Within each window frame a block of either 13 bits (output mode: INT + IFC, REN, EOI, ATN data bit 8 through data bit 1) or 12 bits (input mode: INT + VALDA, bit CO1, bit C02, data bit 8 through data bit one) is "divided" by a polynominal of the fifth power and the remainder is sent along with the data bits. The 18 bit (or 17 bit) message is divided by the same polynominal at the receiving end. If the remainder is not equal to zero, an error is detected and the OK bit is set to false. This polynominal error check is well known in the art (See e.g. the book "Teleprocessing Network Organization" by James Martin, Prentice-Hall, Englewood Cliffs, N.J. 1970).

The following tables give the definitions of the bits sent out by controller and terminal.

I. Data Transmission from Controller to Terminal Bit No. Meaning: 1, 2 : Synchronizing bits; allow the local terminal clock to correct any phase slippage since the original sync. message.

3, 4 : Direction bits; tell the terminal whether that particular window must be used for input or output.

5 through 8 : Service bits for standard interface 9 through 16 : 8 data bits 17 through 21 : Remainder of the division by the polynominal 23, 24, 25 : Acknowledgement (3 bits for covering the maximum time delay) 22, 26 through 28 : Spare time for turn-around II. Data Transmission from Terminal to Controller Bit No. Meaning: 1 through 4 : Same as in table I.

5 . Spare time for turn-around 6, 7 : Backward Synchronizing bits; temporarily synchronize the controller's receiver.

8 : Service bit; indicates whether the data bits from the terminal must be accepted or disregarded.

VALDA = 1 CO1 = EO1 C02 = ATN VALDA = 0 CO1 = SRQ C02 = 9, 10 : Coded service bits for standard interface 11 through 18 : 8 data bits 19 through 23 : Remainder of the division by the polynominal 26 : Acknowledgement 24 through 28 : Spare time for turn-around It should be noted that the service bits are part of the transmitted character and are not relevant for the present invention.

For the purpose of error checking each bit is sampled eight times on the receiving side.

Some critical bits (SYN, START) are regarded to be valid only if seven consistant consecutive samples are taken. The other bits only go through a majority vote test. That means that each bit is sampled seven times. If a bit has been sampled at least four times as a "1" or a "0" it is given the value "1" or "0", respectively.

The operation of both the controller and the terminals can easily be understood with the help of the flow charts in Figures 5 and 6. respectively. Based on these flowcharts and the above description people skilled in the art are able to design suitable digital circuitry fulfulling the required conditions. This circuitry may be realized with commercially available counters. shift registers, gates, read only memories etc.

It should be noted that controller and terminals each have internal local clocks with a clock frequency of 200 kHz, i.e. eight times the bit transmission rate of 25 kbits/sec. This feature facilitates the eight times sampling of each bit.

Mutual synchronizing of the local clocks is not necessary. Due to the synchronizing signals at the beginning of each window frame, long time phase shift due to frequency differences between the terminal clock and the controller clock is uncritical. Since the clock frequency is eight times the bit transmission rate. each resynchronization of the terminal is made with a precision of 1/8 of a bit which is sufficient for this purpose.

WHAT WE CLAIM IS: l. A system for linking data transmitting and receiving devices, comprising: a single channel formed by a serial data transmission line arrangement for interconnecting all

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (1)

1. **WARNING** start of CLMS field may overlap end of DESC **.

   The following tables give the definitions of the bits sent out by controller and terminal.

   I. Data Transmission from Controller to Terminal Bit No. Meaning: 1, 2 : Synchronizing bits; allow the local terminal clock to correct any phase slippage since the original sync. message.

   3, 4 : Direction bits; tell the terminal whether that particular window must be used for input or output.

   5 through 8 : Service bits for standard interface 9 through 16 : 8 data bits 17 through 21 : Remainder of the division by the polynominal 23, 24, 25 : Acknowledgement (3 bits for covering the maximum time delay) 22, 26 through 28 : Spare time for turn-around II. Data Transmission from Terminal to Controller Bit No. Meaning: 1 through 4 : Same as in table I.

   5 . Spare time for turn-around 6, 7 : Backward Synchronizing bits; temporarily synchronize the controller's receiver.

   8 : Service bit; indicates whether the data bits from the terminal must be accepted or disregarded.

   VALDA = 1 CO1 = EO1 C02 = ATN VALDA = 0 CO1 = SRQ C02 = 9, 10 : Coded service bits for standard interface 11 through 18 : 8 data bits 19 through 23 : Remainder of the division by the polynominal 26 : Acknowledgement 24 through 28 : Spare time for turn-around It should be noted that the service bits are part of the transmitted character and are not relevant for the present invention.

   For the purpose of error checking each bit is sampled eight times on the receiving side.

   Some critical bits (SYN, START) are regarded to be valid only if seven consistant consecutive samples are taken. The other bits only go through a majority vote test. That means that each bit is sampled seven times. If a bit has been sampled at least four times as a "1" or a "0" it is given the value "1" or "0", respectively.

   The operation of both the controller and the terminals can easily be understood with the help of the flow charts in Figures 5 and 6. respectively. Based on these flowcharts and the above description people skilled in the art are able to design suitable digital circuitry fulfulling the required conditions. This circuitry may be realized with commercially available counters. shift registers, gates, read only memories etc.

   It should be noted that controller and terminals each have internal local clocks with a clock frequency of 200 kHz, i.e. eight times the bit transmission rate of 25 kbits/sec. This feature facilitates the eight times sampling of each bit.

   Mutual synchronizing of the local clocks is not necessary. Due to the synchronizing signals at the beginning of each window frame, long time phase shift due to frequency differences between the terminal clock and the controller clock is uncritical. Since the clock frequency is eight times the bit transmission rate. each resynchronization of the terminal is made with a precision of 1/8 of a bit which is sufficient for this purpose.

   WHAT WE CLAIM IS: l. A system for linking data transmitting and receiving devices, comprising: a single channel formed by a serial data transmission line arrangement for interconnecting all

   devices involved; a controller connected to said line arrangement and being capable of communicating therewith during successive time multiplex polling cycles each polling cycle starting with a synchronizing message from the controller followed by a plurality of communication time windows; and a plurality of stations connected in parallel across said line arrangement and being capable of independently communicating with said controller via said line arrangement during selected time windows, the single channel formed by the line arrangement permitting communication in both directions between each station and the controller, each station comprising addressing means including an internal address counter and a gating means, said address counter being capable of counting to a preselected value in response to every received synchronizing message from said conctroller and of opening said gating means for the duration of one time window each time after having reached said value, said gating means allowing communication between said station and the controller during said one time window, and the preselected value of the address counter in each station being such that the time window of each station is substantially synchronous with a different one of the communication time windows of the controller's polling cycle, the controller and the stations thereby interfacing the data transmitting and receiving devices with the link system.

   2. A system according to claim 1, characterized in that additional synchronizing signals are transmitted during each time window from the controller to the station and/or vice versa, respectively, in connection with transmitted data, for exactly synchronizing the data receiving station to the data transmitting controller and/or vice versa, respectively, irrespective of the delay times due to the length of the line arrangement.

   3. A system according to claim 1 or 2, characterized in that acknowledgement messages are transmitted upon received data from the station to the controller or vice versa, said acknowledgement messages consisting of bit patterns which are recognizable, irrespective of the delay times due to the length of the line arrangement.

   4. A system according to any one of the preceding claims, characterized in that each station is enabled for communication with the controller only upon an initial synchronizing signal at the beginning of each time window associated to said station.

   5. A system according to any one of the preceding claims, characterized in that an error detecting code is transmitted together with the transmitted data bits.

   6. A system according to any one of the preceding claims, characterized in that each bit received by the station and/or controller is sampled by a plurality of times and that the majority of either one or zero samples is used to decide whether said bit is a one or a zero.

   7. A system according to claim 6, characterized in that a predetermined number of successive similar samples is used to decide in the case of particularly important bits.

   8. A system for linking data transmitting and receiving devices substantially as described with reference to the accompanying drawings and substantially as illustrated in the accompanying drawings.