DE2823709A1 - METHOD FOR TIME MULTIPLEX TRANSMISSION OF DATA FROM ANALOG SIGNALS IN A BUS SYSTEM - Google Patents

Description

VDO 6 FRANKFURT / MAIN 90

ADOLF SCHINDLING AG GRÄFSTRASSE 103

Method for time-multiplexed transmission of data analog signals in a bus system

The invention relates to a method for time-division multiplexed transmission of data from analog signals in a bus system with several participants connected to a bus line with a transmitting and receiving part in which the sequence of all predetermined combinations of the participants is traversed during a time frame and for the connection each combination has at least one time slot available within the time frame, with in the time slots Pulses are transmitted and in particular the time slots by using at least one programmable Counters are formed in each participant, which is counted up with clock pulses, when at least one is reached programmed number emits a control signal and after reaching a predetermined counting capacity that is the same for all counters resets to zero, whereby the control signal establishes a data-transmitting connection between the bus line and a data source or sink for this subscriber is established and the counters of all subscribers are synchronized with each other.

The prior art includes methods for time-division multiplex transmission of data in serial bus systems in which on a bus line, data are transmitted in a predetermined sequence between predetermined participants. While two participants or a predetermined group of participants are connected via the bus line for data transmission, other participants are not allowed to transmit any data to this bus line. In bus systems of this type, a variable time period for information transmission can be permitted for each participant if every participant is set up to

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to output an end signal after transferring its information to the bus line. Otherwise it will be with fixed time periods the serial data transmission worked, whereby the structure of the bus system can be simplified. - To With this method, both analog signals and so-called discrete signals can be transmitted, which only contain yes / no information include. - To control the data transfer between the individual participants of the bus system, belongs In this context, it is related to the prior art that the transmission part of a subscriber, which is responsible for sending Dpten is intended to send an address signal before sending the information, which only the desired other participant or the desired other group of participants transmit the information for further processing in this participant leaves. The end of this transmission is indicated by an end signal on the bus line, which indicates the next Participants or the next group of participants to be sent your information with the preceding address signal and the following end signal.

In order to improve the relative time duration in relation to the total time in which the actually usable information is transmitted, and thus to increase the transfer performance at a given transmission speed of the bus system, it has already been proposed that the time slots be calculated by using at least one programmable counter formed in each participant, which is counted up with clock pulses, when Zrrx-irhen at least one programmed Zrhi emits a control signal and resets itself to zero after reaching a predetermined counting capacity that is the same for all counters, v; obei by the control signal a data transmitter. de Verbin. -unr -vitohen the bus line and a data source or sink of this participant is established and the counters of all participants are synchronized with one another.

According to this proposed method are in the time slots

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for the transmission of the data of analog signals impulses can be transmitted, the duration of which depends on the analog value.

In order to enable the data of analog signals to be transmitted with pulse duration modulated pulses independently of the transmission properties of the bus system, in particular the bus line, additional measures have been proposed which essentially consist in a time interval to the pulse containing the analog value Reference pulse is transmitted and that the pulse and the reference pulse of a ratio of this pulse ^ / forming stage is fed. In particular, a pulse whose duration is the complementary value of the duration of the pulse containing the analog value can be used as the reference pulse. Instead, a pulse can also be used as the reference pulse, the duration of which is 100 % of the maximum possible duration of the pulse containing the analog value.

Albeit the transfer of data discussed above analog signals in connection with the preferred method of forming time slots within a time frame a satisfactory transmission of analog signals or of analog values with a high proportion of usable information for the total transmission time, the influence of the transmission properties, in particular the bus line, on the accuracy of the received "= rte no matter how great, that additional measures associated with additional expenditure must be taken, which are presented above in order to achieve a sufficiently good accuracy of the transmission for many applications.

The present invention is based on the object of multiplexing the known and proposed methods Transmission of data from analog signals or from

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To improve analog values while avoiding the disadvantages of this method in such a way that with the least possible effort regardless of the transmission properties of the bus system, in particular the bus line, the transmission the analog values are sufficiently accurate.

According to the invention, this object is achieved for a method of the type mentioned at the outset in that the analog signal - or the analog value to be transmitted - in a sending participant in one multiple bit comprehensive binary word, which is converted in several successive time slots during which the sending participant is in a data-transmitting connection with at least one receiving participant, bit by bit is transmitted.

This transmission method can advantageously be implemented with sufficient accuracy for all requirements with little hardware outlay, namely practically independent of the transmission properties of the bus system and in particular of the bus line. The accuracy of the transmission is not subject to any fluctuations over time. Another advantage is that arrangements can be used to implement this method which are set up for the transmission of discrete signals and which can be modified for the transmission of analog values without further intervention. It is advantageously ^r V. else also possible to set in a bus system, individual subscriber for the transmission of discrete signals and ignalen other subscribers for transmission of analog.

In a particularly advantageous manner, the method is designed in such a way that the analog value is converted into an 8-bit word becomes and in two consecutive time slots

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is transmitted to the receiving participant.

Only two time slots are used here for the transmission of an analog value, which is transmitted with a resolution of 1: 256. In this case, four bits of information are transmitted in two consecutive time slots. Is dei? The time segment available for the transmission of the usable information in relation to the total time for the transmission of the two time slots is favorable.

In order to be able to retain the time slots designed for the transmission of discrete signals in an expedient manner, the so-called useful bit times for "on" and "off" are halved compared to the useful bit times for the transmission of discrete signals Discrete signal is measured, in the present case 4 bits are transmitted as part of the binary word that contains the analog value.

In the receiving subscriber or in the group of receiving subscribers, the data of the analog Signals that are transmitted in digital form in accordance with the above invention are digitally processed directly or the method is expediently designed in such a way that this occurs in the receiving participant received binary word is converted back into an analog signal.

Thus, analog signals can be recorded in the transmitter, which are transmitted digitally, and then ground again can be reproduced as analog signals in the receiving subscriber in order to feed facilities intended for Processing of analog signals are set up.

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An arrangement for exercising the method for time division multiplexing Data transmission with a transmission output stage, in which the data to be transmitted are in binary form Signals can be fed in is expediently structured with the characteristics that the analog signals generate Data source is connected to a first input of a! Comparator that an output of the comparator is connected via a switching element fed with clock pulses to an input of a counter, one of which Counter output via a shift register with the transmission output stage and that the counter output is connected to a second via a digital / analog converter Input of the comparator is connected.

With this arrangement, which is relatively inexpensive and can be accommodated on a circuit card with a monolithic converter, an analog signal is converted exactly into digital data which is passed to the transmission stage. The conversion takes place in such a way that clock pulses are paid into the counter until the digital value stored in the counter, which is converted into an analog comparison signal by the digital / analog converter, corresponds to the analog signal to be transmitted. The count value counted up in the counter is then sent to a shift register via the subscriber's transmission stage er.r ^ e.-peist. The E-nc.ende subscriber with the transmission stage can, as proposed for the transmission of discrete signals, be designed in such a way that in the subscriber with a control output of a counter switching chain! are connected to generate a time frame synchronization pulse when resetting to zero, which are connected to the bus line via the transmission stage. Furthermore, the transmission stage is connected to a circuit arrangement for generating the time slot synchronization pulses, which is also controlled by the counter.

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The transmitter then sends between two time frame synchronization pulses, between which a series of time slots is formed within a time slot for transmission The digital data in a timeslot is made up of a series of pulses corresponding to the number of times in that timeslot corresponds to the bit to be transmitted, and in the next time slot further pulses that the further or remaining Bits correspond. The time slots are separated from each other by a time slot synchronization pulse »

Furthermore, the arrangement is to be carried out on the receiving side of the method for time-division multiplexed data processing with an output stage of a receiving part that is used for delivery the received data is set up as "impulses," with the characteristics that are implemented at the output stage Shift register is connected, which is preferably connected via a memory with a digital / analog converter stands.

The receiving section feeds clocked pulses which contain the binary data into the shift register. When all the pulses belonging to a binary word are stored in the shift register, this word preferably via a memory that serves as a buffer in a digital / analog converter converted into an analog signal that is the transmitted digital signal and the original analog signal. - There are measures in the receiving participant made sure that only the impulses representing the user data, which go to a raw '.. "place, in the shift register be directed. For this purpose, the output stage of the receiving subscriber and the receiving stage, a switching element is arranged, the. By a receiving address counter is controlled. - The entire additional arrangement for converting the received pulses to a binary one

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Word belonging to an analog signal can, in turn, be comparatively little costly with a monolithic one Converter can be accommodated on an additional circuit card.

The above additional arrangement for forming the analog signal is expediently provided with the feature designed so that the digital / analog converter is connected to an adjustable supply voltage source, from which the analog signal is derived. With this adjustable supply voltage source, an assignment between the maximum analog value and a specific analog value for a full scale of a display instrument can be set.

The invention is illustrated by means of a drawing four figures explained. It shows:

1 shows a pulse diagram on the bus line,

Fig. 2 is a block diagram of a participant, a direct bus module, without means for analog / digital and digital / analog conversion,

3 shows an additional circuit arrangement for the direct bus module for analog signal transmission to Transmission part, and

4 shows an additional circuit arrangement for the direct bus module for analog signal transmission from the Receiving part.

According to FIG. 1, all produce connected to a bus line Participant a time frame synchronization pulse - frame synch - to which a series of η time

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slot up to the second time frame synchronization pulse - Frame Synch - connects. Each time slot is for data transmission between at least two predetermined participants provided. The end of each time slot is indicated by a time slot synchronization pulse - Slot Synch - displayed on the bus line. Between two time slot synchronization pulses or between the first time frame synchronization pulse and the following time slot synchronization pulse takes place Transmission of the analog signals, which are fed into a receiving subscriber, for removal of the turn analog signals from a receiving participant in digital form. This is done within the first time slot 4 bits are provided, and within the subsequent second time slot also 4 bits, that is a total of 8 bits, which together form a binary word, which is the analog signal in digital form with 8 binary parts represents. The binary digits are transmitted as useful data in pulses, with the "High" or "Low" state can occur with each pulse.

In Fig. 1, the time frame synchronization pulses are relatively long and the relatively short time slot synchronization pulses hatched for emphasis.

The duration of each time slot is the same as for the transmission of analog values in digital form the duration of the time slot for discrete value transmission, in which only two usable pulses between two time slot synchronization pulses be transmitted. The transmission of the impulses for the digital data, which which represent analog signals is controlled by clock pulses whose frequency is twice as high as in the case of the transmission of discrete signals.

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In Fig. 2, a participant is shown with a transmitting and a receiving part, which per se for transmission of discrete signals is set up via the bus line, but according to the invention for the transmission of analog signals Signals can be added so that the analog signals are transmitted as the same digital data over the bus line will.

The participant includes a clock generator 1, the clock pulses generated, which are fed into a counting input 2 of an address counter and decoder 3. The address counter and decoder serves both as a send address counter and as a receive address counter. A reset input of the address counter and decoder is denoted by 4. Df.r address counter and decoder is through connections (pins) 5 externally programmable in such a way that when reached Two signals appear at a control output 6 from two programmed numbers through exponents. Besides that the address counter and decoder in conjunction with a time frame synchronization generator 10 forms a signal, when the address counter 3 is reset to zero. Finally, the address counter generates 3 in conjunction with the time slot synchronization generator 11 Signal at the end of each time slot.

The control output 6 of the address counter 3 is connected to a switching element AND element via an S> 3: NEXT / RECEIVING switch 7 on the one hand - 9 connected, which to the receiving part belongsj and on the other hand to a transmission stage S. The Transmission stage 8 is also associated with the time frame synchronization generator 10 and the Zeixs ^ hlitzp ^ .- l.rrnisationsgenerator 11 via an OR gate 12 in connection.

The data input of the subscriber fed by the bus line 13 begins with a receiving stage 14, from which means a synchronization detector 15 synchronization pulses

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are taken, which via lines 16, 17 in the Clock generator 1 and the address counter 3 are fed. This means that when time slot synchronization pulses occur or time frame synchronization pulses do not emit clock pulses from the clock generator 1, and the clock generator is synchronized with synchronization pulses on the bus line.

The transmission stage 8 is via a storing input circuit arrangement with a signal generator in connection, which the signals as impulses, the discrete signals with the States "high" and "low", feeds into the input circuitry. The input circuitry 18 can be controlled via a control line 19.

A receiving line emanating from the receiving stage 14 20 is led via the switching element 9 to a memory 21 in which the useful data transmitted by the bus line can be stored in pulses. A memory output 22 is connected to a driver stage 23, which is pulsed Outputs switching states "On" and "Off".

A subscriber according to FIG. 2 is controlled to operate for the transmission of data of analog signals that ■ in transmission mode sends out 4 bits each and a maximum of 4 pulses in two successive time slots that lead to a binary input serially fed into the input circuit arrangement 18 8 bits belong.

In the receiving mode, the switching element 9 is controlled in such a way that the memory 21 is able to receive 4 bits in two consecutive time slots with the receiving leix-img 20 is connected, so that a binary word consisting of 8 bits is formed in the memory 21.

In Fig. 3 connection terminals of an analog input

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voltage representing the analog signal, denoted by 24. The input terminal 24 is with the first Connected to input 26 of a comparator 27, which acts as a DC voltage comparator is trained. A connection leads from the output 28 of the comparator via a switching element 29, which is acted upon by clock pulses at a terminal 30, to an input 31 of a counter Storage locations for storing 8 bits. A connection leads from the counter output 33 to a shift register 34, which is also set up to accept 8 bits. The shift register has output lines 35, 36, which lead to the input circuit 18 of the transmission stage 8 in FIG.

From the counter output 33 a connection to a digital / analog converter 37 branches off, the output 38 of which is connected to it a second input 39 of the comparator is connected.

The additional circuit arrangement for the transmission of analog Signals with the discrete bus module according to FIG. 1 works in such a way that in the counter 32 via the switching element 29 clock pulses are fed in until the analog input voltage at terminal 24 corresponds to the analog comparison signal at output 38 of the analog / digital converter, i.e. is equal. In this case, a binary »location consisting of 3 bits is counted into the counter, the is equal to the analog input voltage. The binary V.'ort is transferred from the counter 32 to the shift register 34 for serial output to the input circuit 18. That The 8-bit '..' location is split into two with the transmission level successive time slots on the bus line 13 in FIG.

The additional circuit arrangement in FIG. 4 for analog signal transmission by means of a discrete bus module according to FIG to convert the lines 40, 41 from the driver

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stage 23 in Fig. 2 emitted pulses, which form a word of 8 bits, into an analog signal at the terminals 42, 43 formed.

For this purpose, lines 40, 41 are connected to inputs 44, 45 of a shift register 46, which is used for serial parallel conversion which is used for the pulses fed into the shift register. That in the shift register 8-bit word is transferred via a buffer 47 to a digital / analog converter 48, which is a the digital value of the binary word in the shift register proportional, preferably the same analog Output voltage signal generated at terminals 42, 43, in connection with the driver 48a fed by it To assign the maximum analog value to a specific one Analog value or for setting a full scale of one connected to terminals 42, 4J- Instruments is an adjustable supply voltage source, which consists of a voltage divider 49, 50 and a stabilizing Diode 51 is made.

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Claims (6)

VDO 6 FRANKFURT / MAIN 90 ADOLF SCHINDLING AG GRÄFSTRASSE 103 Pa t en t claims Method for the time-division multiplex transmission of data of analog signals in a bus system with several participants connected to a bus line with a transmitting and receiving part, in which the sequence of all specified combinations of participants is run through during a time frame and for the connection of each combination at least one time slot is available within the time frame, pulses are transmitted in the time slots and v / obei in particular the time slots are formed by using at least one programmable counter in each participant, which is counted up with clock pulses, emits a control signal when at least one programmed number is reached and resets itself to zero after reaching a predetermined counting capacity that is the same for all counters, with a data-transmitting connection between the bus line and a data source or sink of this participant being established by the control signal, and the z hler all participants are synchronized with each other, characterized in that the analog signal to be transmitted is converted in a sending participant into a binary V / orx comprising several bits, which in several successive time slots, during which the sending participant with at least one receiving participant in data-transmitting Connection is established, is transmitted bit by bit. 2. The method according to claim 1, characterized in that the analog value is converted into an 8-bit word and is transmitted to the receiving subscriber in two successive time slots. 909849/0183 ORIGINAL INSPECTED 3. Method according to claim 1 or 2, characterized in that the binary word received in the receiving subscriber is converted back into an analog signal. 4. An arrangement for performing the method for time-division multiplexed data transmission with a transmission output stage, into which the data to be transmitted can be fed as binary signals, according to claim 1 or 2, characterized in that the data source generating the analog signals is connected to a first input (26) of a Comparator (27) is connected that an output (28) of the comparator is connected via a switching element (29) fed with clock pulses to an input (31) of a counter (32), of which a counter output (33) is connected via a shift register (34 ) mix of the transmission stage is connected and that the counter output (33) is connected to a second input (39) of the comparator (27) via a digital / analog converter. 5. Arrangement for carrying out the method for time-division multiplex data transmission with an output stage of a receiving part, which is set up to output the received data as pulses, according to claim 3, characterized in that a shift register (46) is connected to the output stage (driver stage 23), which is preferably connected to a digital / analog converter (48) via an intermediate memory (47). 6. Arrangement according to claim 5, characterized in that the digital / analog converter (48) is connected to an adjustable supply voltage source (49, 50, 51) from which the analog signal is derived. 909849/0183