RU2813010C1 - High-speed operational amplifier based on complementary bent cascades - Google Patents

Abstract

FIELD: radio electronics.

SUBSTANCE: operational amplifier is proposed, the circuit of which includes the first (16), second (17), third (18) and fourth (19) additional transistors, the first (20) additional current-stabilizing two-terminal network, the second (21) additional current-stabilizing two-terminal network, the third (22) additional current-stabilizing two-terminal network, the fourth (23) additional current-stabilizing two-terminal network, and the emitter of the first (16) additional transistor is connected to the emitter of the fourth (19) additional transistor through the first (24) additional correction capacitor, the emitter of the second (17) additional transistor is connected to the emitter the third (18) additional transistor through the second (25) additional correction capacitor, and the collectors of the third (18) and fourth (19) additional transistors are connected to the input of the buffer amplifier (12).

EFFECT: providing higher levels of output current in the structure of the intermediate stage of the operational amplifier, which recharges the integrating correction capacitor of the op-amp during the front of the transient process.

1 cl, 10 dwg, 2 tbl

Description

The invention relates to radio electronics and can be used as operational amplifiers (op-amps), intended for use in the subclass of so-called discrete-analog SC filters on switched capacitors [1-2], which (in a number of important cases) require increased values of the maximum the rate of rise of the output voltage of the op-amp, as well as in the drivers of high-speed analog-to-digital converters.

In modern electronic equipment, operational amplifiers based on bipolar [3-20] and field-effect [21-24] transistors are used, based on the architecture of a push-pull complementary “bent cascode”. Their main advantages are an extended frequency range, as well as efficient use of supply voltage. However, this class of known op-amps [3-24] does not solve the problem of significantly increasing the maximum rate of rise of the output voltage (SR).

As shown in [25-27], the performance of classical operational amplifiers with single-pole frequency correction by one integrating capacitor ( _Ck ) is determined by the range of active operation of the input stage. To increase the maximum speed of the output voltage of an op-amp (SR) with a classical architecture, as a rule, special nonlinear correction circuits are provided, providing high levels of output currents in the dynamic overload mode of the op-amp input stage, which contributes to a faster recharge of the integrating correction capacitance C _to [25-27 ]. However, for the class of op-amp under consideration based on push-pull complementary “bent cascodes” [3-24], such circuits have not been developed. This problem is solved in the circuit solution proposed below.

The closest prototype (Fig. 1) of the claimed device is the operational amplifier according to US patent 4.837.523, fig. 1, 1989. The op-amp prototype contains (Fig. 1) a differential input stage 1 with the first 2 and second 3 inputs, as well as the first 4 and second 5 current outputs, matched respectively with the first 6 and second 7 power supply buses, the first 4 current output is connected to the emitter of the first 8 output transistor, which is connected to the first 6 power supply bus through the first 9 reference current source, the second 5 current output is connected to the emitter of the second 10 output transistor, which is connected to the second 7 power supply bus through the second 11 source reference current, the combined collectors of the first 8 and second 10 output transistors are connected to the input of the buffer amplifier 12 and the correction capacitor 13, the base of the first 8 output transistor is connected to the first 14 bias voltage source, and the base of the second 10 output transistor is connected to the second 15 bias voltage source.

A significant drawback of the known op-amp Fig. 1 is that the maximum output current of the push-pull “bent” cascode (in the dynamic overload mode of the input stage 1) is rigidly connected with the currents of the first 9 and second 11 reference current sources. This does not allow, with low static current consumption, to quickly recharge the integrating correction capacitor 13 (C _to =C ₁₃ ), which ensures the stability of the circuit, which limits the maximum rate of rise of the output voltage in an op-amp of this class [25-27].

The main objective of the proposed invention is to provide higher levels of output current of the push-pull “bent cascode” I _out.max , recharging the correction capacitor op-amp 13 (C _to =C ₁₃ ) during the front of the transient process. Ultimately, this increases the performance of the op-amp in large-signal mode and reduces the settling time of the transient process [25-27].

This task is achieved by the fact that in the operational amplifier of Fig. 1, containing an input differential stage 1 with the first 2 and second 3 inputs, as well as the first 4 and second 5 current outputs, matched, respectively, with the first 6 and second 7 power supply buses, the first 4 current output is connected to the emitter of the first 8 output transistor, which is connected to the first 6 power supply bus through the first 9 reference current source, the second 5 current output is connected to the emitter of the second 10 output transistor, which is connected to the second 7 power supply bus through the second 11 source reference current, the combined collectors of the first 8 and second 10 output transistors are connected to the input of the buffer amplifier 12 and the correction capacitor 13, the base of the first 8 output transistor is connected to the first 14 bias voltage source, and the base of the second 10 output transistor is connected to the second 15 bias voltage source, new elements and connections are provided - the first 16, second 17, third 18 and fourth 19 additional transistors are introduced into the circuit of Fig. 2, the base of the first 16 additional transistor is connected to the emitter of the first 8 output transistor, its emitter is connected to the first 6 bus of the power source through the first 20 is an additional current-stabilizing two-terminal network, and the collector is matched to the second 7 bus of the power source, the base of the second 17 additional transistor is connected to the emitter of the second 10 output transistor, its emitter is connected to the second 7 bus of the power source through the second 21 additional current-stabilizing two-terminal network, and the collector is matched to the first 6 power supply bus, the base of the third 18 additional transistor is connected to the first 14 bias voltage source, its emitter is connected to the first 6 power supply bus through the third 22 additional current-stabilizing two-terminal network, the base of the fourth 19 additional transistor is connected to the second 15 bias voltage source, its emitter is connected to the second 7 power supply bus through the fourth 23 additional current-stabilizing two-terminal network, and the emitter of the first 16 additional transistor is connected to the emitter of the fourth 19 additional transistor through the first 24 additional correction capacitor, the emitter of the second 17 additional transistor is connected to the emitter of the third 18 additional transistor through the second 25 additional correction capacitor , and the collectors of the third 18 and fourth 19 additional transistors are connected to the input of the buffer amplifier 12. The output 26 of the buffer amplifier 12 is the potential output of the device.

In the drawing FIG. Figure 1 shows a circuit of an operational amplifier - a prototype based on complementary “bent” cascodes on the first 8 and second 10 output transistors.

In the drawing FIG. Figure 2 shows the circuit of the claimed op-amp in accordance with claim 1 of the claims for the first particular case of implementing the input differential stage 1 on transistors 27, 28, 30, 31 and reference current sources 29 and 32 (I ₂₉ , I ₃₂ ).

In the drawing FIG. Figure 3 shows a diagram of the proposed op-amp in accordance with claim 1 of the claims for the second particular case of the implementation of the input differential stage 1, which is made on transistors 27, 28, 30, 31, 33 and 34 and reference current sources 29 and 32. Introduction of transistors 33 and 34 makes it possible to reduce the systematic component of the op-amp zero bias voltage by “leveling” the static base-collector voltages of the corresponding pairs of transistors 27, 28 and 30, 31.

In the drawing FIG. Figure 4 shows the static mode of the op-amp of Fig. 2 in the LTSpice environment on transistor models of the base matrix crystal MH2XA031_01/25/21 at 27°C, reference current sources I ₁ =I ₂ =I ₇ =I ₈ =300 μA, I ₅ =I ₆ =400 μA, I ₃ =I ₄ =100 µA, integrating correction capacitor 13 (C _to =C ₁ =C ₁₃ =1 pF), additional correction capacitors 24 and 25 (C _{to 1} =C ₂₄ =C _{to 2} =C ₂₅ =0 pF), power buses V1 = V2 =±10 V.

In the drawing FIG. 5 shows the leading edge of the transient process of the op-amp in the drawing of FIG. 4.

In the drawing FIG. 6 shows the trailing edge of the transient process of the op-amp in the drawing of FIG. 4.

In the drawing FIG. Figure 7 shows the static mode of the op-amp of Fig. 2 with current-limiting resistor R1=1kOhm in the LTSpice environment on transistor models of the base matrix crystal MH2XA031_25.01.21 at 27°C, reference current sources I ₁ =I ₂ =I ₇ =I ₈ =300 µA, I ₅ =I ₆ =400 µA , I ₃ =I ₄ =100 μA, integrating correction capacitor 13 (C _to =C ₁ =C ₁₃ =1 pF), additional correction capacitors 24 and 25 (C _{to 1} =C ₂₄ =C _{to 2} =C ₂₅ =0 pF) , voltage on the power bus V1=V2=±10 V.

In the drawing FIG. 8 shows the logarithmic amplitude-frequency characteristics of the voltage gain of the op-amp in the drawing of FIG. 7.

In the drawing FIG. 9 shows the leading edge of the transient process in the op-amp in the drawing of FIG. 7 with current limiting resistor R1.

In the drawing FIG. 10 shows the trailing edge of the transient process in the op-amp in the drawing of FIG. 7 in the presence of current-limiting resistor R1.

High-speed operational amplifier based on complementary “bent” cascodes Fig. 2 contains an input differential stage 1 with the first 2 and second 3 inputs, as well as the first 4 and second 5 current outputs, matched respectively with the first 6 and second 7 buses of power supplies, and the first 4 current output is connected to the emitter of the first 8 output transistor, which through the first 9 reference current source is connected to the first 6 power supply bus, the second 5 current output is connected to the emitter of the second 10 output transistor, which is connected to the second 7 power supply bus through the second 11 reference current source, the combined collectors of the first 8 and second 10 output transistors connected to the input of the buffer amplifier 12 and the correction capacitor 13, the base of the first 8 output transistor is connected to the first 14 bias voltage source, and the base of the second 10 output transistor is connected to the second 15 bias voltage source. The first 16, second 17, third 18 and fourth 19 additional transistors are introduced into the circuit, the base of the first 16 additional transistor is connected to the emitter of the first 8 output transistor, its emitter is connected to the first 6 bus of the power source through the first 20 additional current-stabilizing two-terminal network, and the collector is matched with the second 7 bus of the power source, the base of the second 17 additional transistor is connected to the emitter of the second 10 output transistor, its emitter is connected to the second 7 bus of the power source through the second 21 additional current-stabilizing two-terminal network, and the collector is matched to the first 6 bus of the power source, the base of the third 18 additional transistor connected to the first 14 bias voltage source, its emitter is connected to the first 6 power supply bus through the third 22 additional current-stabilizing two-terminal network, the base of the fourth 19 additional transistor is connected to the second 15 bias voltage source, its emitter is connected to the second 7 power supply bus through the fourth 23 additional current-stabilizing two-terminal network, and the emitter of the first 16 additional transistor is connected to the emitter of the fourth 19 additional transistor through the first 24 additional correction capacitor, the emitter of the second 17 additional transistor is connected to the emitter of the third 18 additional transistor through the second 25 additional correction capacitor, and the collectors of the third 18 and fourth 19 additional transistors are connected to the input of the buffer amplifier 12. The output 26 of the buffer amplifier 12 is the potential output of the device.

In addition, in the diagram of Fig. 3, the input differential stage 1 contains auxiliary transistors 33, 34, the bases of which are connected, respectively, to the emitter of the first 16 and the emitter of the second 17 additional transistors. This circuit design balances the static mode of transistors 27, 28, as well as transistors 30, 31 in terms of collector-base voltages. As a consequence, this reduces the systematic component of the zero offset voltage, due to the influence of the internal feedback coefficient of transistors 27-28 and 30-31.

Let's consider the operation of the op-amp of Fig.2.

Static mode of transistors in the circuit of Fig. 2 is provided by the first 9 and second 11 reference current sources, the third 22, fourth 23, first 20 and second 21 additional current-stabilizing two-terminal networks, as well as reference current sources 32 and 29. The currents of the first 9 and second 11 reference current sources are selected less than the currents of the sources reference current 32 and 29.

With a large pulse change in the input voltage at the first 2 input of the op-amp Fig. 2 the second 10 output transistor is turned off, and the voltage at the base of the second 17 additional transistor increases, which creates an additional pulse current through the second 25 additional correction capacitor, which is transmitted to the emitter of the third 18 additional transistor and then to the correction capacitor 13, which contributes to its faster recharge .

With a negative pulse voltage change at input 1, the voltage at the base of the first 16 additional transistor increases, which generates a pulse current through the first 24 additional correction capacitor. This current is transmitted to the emitter of the fourth 19 additional transistor and then to the correction capacitor 13. Due to the above transient processes, the maximum rate of rise of the op-amp output voltage increases significantly (see tables 1, 2, as well as graphs of Fig. 5, Fig. 6).

Table 1 - Dependencies of SR op-amp Fig. 4 from the capacitances of the first 24 (C ₂₄ =C _k1 ) and second 25 (C ₂₅ =C _k2 ) additional correction capacitors Capacitor Capacitance Values
Sk1, Sk2 in the diagram of Fig. 4 SR ⁽⁺⁾ leading edge SR ^(-) trailing edge C _k1 = Sk2 = 0 pF 248.7 V/µs 243.5 V/µs C _k1 = Sk2 = 50 pF 4148.1 V/µs 3294.1 V/µs

Table 2 - Dependences of SR op-amp with current-limiting resistor R1=1 kOhm (Fig. 7) on the capacitances of the first 24 (C ₂₄ =C _k1 ) and second 25 (C ₂₅ =C _k2 ) additional correction capacitors Capacitor Capacitance Values
Sk1, Sk2 in the diagram of Fig. 7 SR ⁽⁺⁾ leading edge SR ^(-) trailing edge C _k1 = Sk2 = 0 pF 245.8 V/µs 239.3 V/µs C _k1 = Sk2 = 10 pF 3353.3 V/µs 1931.1 V/µs

Analysis of Table 2, as well as the graphs of the transient process in Fig. 9, fig. 10 shows that by introducing a current-limiting resistor R1, it is possible to reduce the overshoot of the transient process while maintaining the maximum rate of rise of the output voltage at a sufficiently high level.

Thus, the claimed device has significant advantages in comparison with the prototype op-amp in terms of the maximum rate of rise of the output voltage of a closed-loop op-amp.

BIBLIOGRAPHICAL LIST

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Claims (1)

A high-speed operational amplifier based on complementary “bent” cascodes, containing an input differential stage (1) with the first (2) and second (3) inputs, as well as the first (4) and second (5) current outputs, matched respectively with the first (6 ) and the second (7) power supply buses, wherein the first (4) current output is connected to the emitter of the first (8) output transistor, which is connected through the first (9) reference current source to the first (6) power supply bus, the second (5) the current output is connected to the emitter of the second (10) output transistor, which is connected to the second (7) power supply bus through the second (11) reference current source, the combined collectors of the first (8) and second (10) output transistors are connected to the input of the buffer amplifier ( 12) and a correction capacitor (13), the base of the first (8) output transistor is connected to the first (14) bias voltage source, and the base of the second (10) output transistor is connected to the second (15) bias voltage source, characterized in that in the circuit the first (16), second (17), third (18) and fourth (19) additional transistors are introduced, the base of the first (16) additional transistor is connected to the emitter of the first (8) output transistor, its emitter is connected to the first (6) source bus power supply through the first (20) additional current-stabilizing two-terminal network, and the collector is matched to the second (7) power supply bus, the base of the second (17) additional transistor is connected to the emitter of the second (10) output transistor, its emitter is connected to the second (7) power supply bus through the second (21) additional current-stabilizing two-terminal network, and the collector is matched to the first (6) power supply bus, the base of the third (18) additional transistor is connected to the first (14) bias voltage source, its emitter is connected to the first (6) power supply bus through the third (22) additional current-stabilizing two-terminal network, the base of the fourth (19) additional transistor is connected to the second (15) bias voltage source, its emitter is connected to the second (7) power supply bus through the fourth (23) additional current-stabilizing two-terminal network, and the emitter of the first (16) ) of the additional transistor is connected to the emitter of the fourth (19) additional transistor through the first (24) additional correction capacitor, the emitter of the second (17) additional transistor is connected to the emitter of the third (18) additional transistor through the second (25) additional correction capacitor, and the collectors of the third ( 18) and the fourth (19) additional transistors are connected to the input of the buffer amplifier (12).