RU2813280C1 - High-speed operational amplifier based on complementary bent cascade - Google Patents

Abstract

FIELD: radio electronics.

SUBSTANCE: operational amplifier is proposed, the circuit of which includes the first (23) and second (24) additional transistors, the first (25) additional current-stabilizing two-terminal network, the first (26) additional correction capacitor, the second (27) additional current-stabilizing two-terminal network, the second (28) additional correction capacitor, and the base of the second (24) additional transistor is connected to the emitter of the third (16) output transistor, the collectors of the first (23) and second (24) additional transistors are connected to the input of the buffer amplifier (19), and the collectors of the first (12) and the third (16) output transistors are connected to the common bus of the first (4) and second (8) power supplies.

EFFECT: during the front of the transient process, ensuring higher levels of the output current of the push-pull complementary bent cascade, which recharges the integrating correction capacitor of the op-amp.

1 cl, 9 dwg, 2 tbl

Description

The invention relates to radio electronics and can be used as operational amplifiers (op-amps), intended for use in the subclass of so-called discrete-analog SC filters on switched capacitors [1-2], which (in a number of important cases) require increased values of the maximum the rate of rise of the output voltage of the op-amp, as well as in the drivers of high-speed analog-to-digital converters.

In modern electronic equipment, operational amplifiers based on bipolar [3-20] and field-effect [21-24] transistors are used, based on the architecture of a push-pull complementary “bent” cascode. Their main advantages are an extended frequency range, as well as efficient use of supply voltage. However, this class of known op-amps [3-24] does not solve the problem of significantly increasing the maximum rate of rise of the output voltage (SR).

As shown in [25-27], the performance of classical operational amplifiers with single-pole frequency correction using a single integrating capacitor ( _Ck ) is determined by the range of active operation of the input stage. To increase the maximum speed of the output voltage (SR) of an op-amp with a classical architecture, as a rule, special dynamic correction circuits for the transient process are provided, which provide high levels of currents that recharge C to in the overload mode of the op-amp input _stage . This contributes to a significant increase in SR [25-27]. However, for the class of op-amps under consideration based on push-pull complementary “bent” cascodes [3-24], such circuits have not been developed. This problem is solved in the circuit solution proposed below.

The closest prototype (Fig. 1) of the proposed device is an operational amplifier described in the monograph “Prokopenko N.N. Architecture and circuit design of high-speed operational amplifiers: monograph / N.N. Prokopenko, A.S. Budyakov. – Mines: YURGUES Publishing House, 2006. – P. 63, fig. 2.18". The op-amp prototype contains (Fig. 1) the first 1 and second 2 inputs of the device, the first 3 input transistor, the emitter of which is connected to the first 4 bus of the power source through the first 5 current-stabilizing two-terminal network and connected to the emitter of the second 6 input transistor, the third 7 input transistor, the emitter of which is connected to the second 8 bus of the power source through the second 9 current-stabilizing two-terminal network and is connected to the emitter of the fourth 10 input transistor, the bases of the first 3 and third 7 input transistors are connected to the first 1 input of the device, the bases of the second 6 and fourth 10 input transistors are connected to the second 2 input device, the collector of the first 3 input transistor is connected to the second 8 bus of the power source through the third 11 current-stabilizing two-terminal network and connected to the emitter of the first 12 output transistor, the collector of the second 6 input transistor is connected to the second 8 bus of the power source through the fourth 13 current-stabilizing two-terminal network and connected to the emitter of the second 14 output transistor, the collector of the third 7 input transistor is connected to the first 4 bus of the power source through the fifth 15 current-stabilizing two-terminal network and connected to the emitter of the third 16 output transistor, the collector of the fourth 10 input transistor is connected to the first 4 bus of the power source through the sixth 17 current-stabilizing two-terminal network and connected to the emitter of the fourth 18 output transistor, the collectors of the second 14 and fourth 18 output transistors are connected to the input of the buffer amplifier 19 and the correction capacitor 20, the bases of the first 12 and second 14 output transistors are connected to the first 21 bias voltage source, and the bases of the third 16 and fourth 18 output transistors connected to the second 22 bias voltage source.

A significant drawback of the known op-amp Fig. 1 is that in the mode of dynamic overload of the input stage on the first 3 and second 6 input transistors or the third 7 and fourth 10 input transistors, the maximum output current of the “bent” cascode is rigidly connected with the currents of the fourth 13 and sixth 17 current-stabilizing two-terminal circuits. This does not allow, given the restrictions on the static current consumption of the op amp, to quickly recharge the integrating correction capacitor 20 (C _to =C ₂₀ ), which ensures the stability of the circuit, which limits the maximum rate of rise of the output voltage in an op amp of this class [25-27].

The main objective of the proposed invention is to provide, during the front of the transient process, higher levels of output current of a push-pull complementary “bent” cascode (I _{output max} ), recharging the integrating correction capacitor op-amp 20 (C _to =C ₂₀ ). Ultimately, this increases the performance of the op-amp in large-signal mode and reduces the settling time of the transient process [25-27].

The task is achieved by the fact that in the operational amplifier of Fig. 1, containing the first 1 and second 2 inputs of the device, the first 3 input transistor, the emitter of which is connected to the first 4 bus of the power source through the first 5 current-stabilizing two-terminal network and is connected to the emitter of the second 6 input transistor, the third 7 input transistor, the emitter of which is connected to the second 8 power supply bus through the second 9 current-stabilizing two-terminal network and is connected to the emitter of the fourth 10 input transistor, the bases of the first 3 and third 7 input transistors are connected to the first 1 input of the device, the bases of the second 6 and fourth 10 input transistors connected to the second 2 input of the device, the collector of the first 3 input transistor is connected to the second 8 power supply bus through the third 11 current-stabilizing two-terminal network and is connected to the emitter of the first 12 output transistor, the collector of the second 6 input transistor is connected to the second 8 power supply bus through the fourth 13 current-stabilizing two-terminal network and is connected to the emitter of the second 14 output transistor, the collector of the third 7 input transistor is connected to the first 4 bus of the power source through the fifth 15 current-stabilizing two-terminal network and is connected to the emitter of the third 16 output transistor, the collector of the fourth 10 input transistor is connected to the first 4 bus of the power source through the sixth 17 current-stabilizing two-terminal network and connected to the emitter of the fourth 18 output transistor, the collectors of the second 14 and fourth 18 output transistors are connected to the input of the buffer amplifier 19 and the correction capacitor 20, the bases of the first 12 and second 14 output transistors are connected to the first 21 bias voltage source, and the bases of the third 16 and the fourth 18 output transistors are connected to the second 22 bias voltage source, new elements and connections are provided - the first 23 and second 24 additional transistors are introduced into the circuit, the emitter of the first 23 additional transistor is connected to the second 8 bus of the power source through the parallel-connected first 25 additional current stabilizing two-terminal network and the first 26 additional correction capacitor, the base of the first 23 additional transistor is connected to the emitter of the first 12 output transistor, the emitter of the second 24 additional transistor is connected to the first 4 bus of the power source through the parallel-connected second 27 additional current-stabilizing two-terminal network and the second 28 additional correction capacitor, and the base of the second 24 additional transistor is connected to the emitter of the third 16 output transistor, the collectors of the first 23 and second 24 additional transistors are connected to the input of the buffer amplifier 19, and the collectors of the first 12 and third 16 output transistors are connected to the common bus of the first 4 and second 8 power sources.

In the drawing FIG. Figure 1 shows a circuit diagram of a prototype operational amplifier. In this circuit, the matching circuit (MC) ensures the transmission of increments in the collector currents of the first 12 and third 16 output transistors to the high-impedance node Σ ₁ .

In the drawing FIG. 2 shows a diagram of the proposed op-amp in accordance with claim 1 and claim 2 of the invention formula.

In the drawing FIG. 3 shows the static mode of the proposed op-amp of Fig. 2 in the LTSpice environment on transistor models of the base matrix crystal MH2XA031_01/25/21 at 27°C, reference current sources I ₁ =I ₂ =400 µA, I ₃ =I ₄ =I ₆ =I ₇ =300 µA, I ₅ =I ₈ =100 µA , correction capacitor 20 (C ₁ =C _to =C ₂₀ =1pF), additional correction capacitors 26 and 28 (C _{to 1} =C ₂₆ =C _{to 2} =C ₂₈ =0pF), power buses V1=V2=±10V.

In the drawing FIG. Figure 4 shows the logarithmic amplitude-frequency characteristics (LAFC) of the op-amp in the drawing of Fig. 3.

In the drawing FIG. 5 shows the leading edge of the transient process in the op-amp of Fig. 3 according to claim 1 of the claims.

In the drawing FIG. 6 shows the trailing edge of the transient process in the op-amp of Fig. 3 according to claim 1 of the claims.

In the drawing FIG. Figure 7 shows the static mode of the op-amp of Fig. 2 according to claim 2 of the claims in the LTSpice environment on transistor models of the base matrix crystal MH2XA031_01/25/21 at 27°C, reference current sources I ₁ =I ₂ =400 μA, I ₃ =I ₄ =I ₆ =I ₇ =300 μA, I ₅ =I ₈ =100 μA, correction capacitor 20 (C ₁ =C _k =C ₂₀ =1pF), additional correction capacitors 26, 28 and 30 (C _k1 =C ₂₆ =C _k2 =C ₂₈ =C _k3 =C ₃₀ = 0pF), power buses V1=V2=±10V.

In the drawing FIG. 8 shows the leading edge of the transient process in the op-amp of Fig. 7 according to claim 2 of the claims.

In the drawing FIG. 9 shows the trailing edge of the transient process in the op-amp of Fig. 7 according to claim 2 of the claims.

A high-speed operational amplifier based on a complementary “bent” cascode Fig. 2 contains the first 1 and second 2 inputs of the device, the first 3 input transistor, the emitter of which is connected to the first 4 bus of the power source through the first 5 current-stabilizing two-terminal network and is connected to the emitter of the second 6 input transistor, the third 7 input transistor, the emitter of which is connected to the second 8 bus power source through the second 9 current-stabilizing two-terminal network and connected to the emitter of the fourth 10 input transistor, the bases of the first 3 and third 7 input transistors are connected to the first 1 input of the device, the bases of the second 6 and fourth 10 input transistors are connected to the second 2 input of the device, the collector of the first 3 input transistor connected to the second 8 bus of the power source through the third 11 current-stabilizing two-terminal network and connected to the emitter of the first 12 output transistor, the collector of the second 6 input transistor is connected to the second 8 bus of the power source through the fourth 13 current-stabilizing two-terminal network and connected to the emitter of the second 14 output transistor, the collector of the third 7 input transistor is connected to the first 4 bus of the power source through the fifth 15 current-stabilizing two-terminal network and connected to the emitter of the third 16 output transistor, the collector of the fourth 10 input transistor is connected to the first 4 bus of the power source through the sixth 17 current-stabilizing two-terminal network and connected to the emitter of the fourth 18 output transistor, collectors the second 14 and fourth 18 output transistors are connected to the input of the buffer amplifier 19 and the correction capacitor 20, the bases of the first 12 and second 14 output transistors are connected to the first 21 bias voltage source, and the bases of the third 16 and fourth 18 output transistors are connected to the second 22 bias voltage source . The first 23 and second 24 additional transistors are introduced into the circuit, the emitter of the first 23 additional transistor is connected to the second 8 bus of the power source through the parallel-connected first 25 additional current-stabilizing two-terminal network and the first 26 additional correction capacitor, the base of the first 23 additional transistor is connected to the emitter of the first 12 output transistor, the emitter of the second 24 additional transistor is connected to the first 4 bus of the power source through a parallel-connected second 27 additional current-stabilizing two-terminal network and a second 28 additional correction capacitor, and the base of the second 24 additional transistor is connected to the emitter of the third 16 output transistor, the collectors of the first 23 and second 24 additional transistors are connected to the input of the buffer amplifier 19, and the collectors of the first 12 and third 16 output transistors are connected to the common bus of the first 4 and second 8 power sources.

In the drawing of Fig.2, in accordance with claim 2 of the claims, the combined emitters of the third 7 and fourth 10 input transistors are connected to the combined emitters of the first 3 and second 6 input transistors through the third 30 additional correction capacitor and an additional current-limiting resistor 31.

Let's consider the operation of the op-amp of Fig.2.

Static mode of transistors of the op-amp circuit Fig. 2 is provided by the first 5, the second 9, the third 11, the fourth 13, the fifth 15, the sixth 17 current-stabilizing two-terminal networks, the first 25 and second 27 additional current-stabilizing two-terminal networks, as well as the first 21 and second 22 bias voltage sources.

The currents of the third 11, fourth 13, as well as the fifth 15 and sixth 17 current-stabilizing two-terminal networks are selected 50-100 μA less than the currents of the second 9 and first 5 current-stabilizing two-terminal networks. With a large pulse change in the input voltage at the first 1 input of the op-amp Fig. 2, the second 6 input transistor is almost instantly turned off, and the voltage at the base of the first 23 additional transistor increases, which generates an additional pulse current through the first 26 additional correction capacitor and the corresponding charge current of the correction capacitor 20.

With a negative pulse change in voltage at input 1, the voltage at the base of the second 24 additional transistor increases, which generates a pulse current through the second 28 additional correction capacitor and an additional collector current of the second 24 additional transistor, forcing the discharge process of the correction capacitor 20. Due to the above transient processes, the maximum maximum rate of rise of the output voltage (Table 1).

Table 1 - Dependencies of the maximum rate of rise of the output voltage of the op-amp Fig. 3 from the capacitances of additional correction capacitors 26 (C _k1 = C ₂₆ ) and 28 (C _k2 = C ₂₈ )

Capacitor capacities
C _k1 = C ₂₆ , C _k2 = C ₂₈ in the diagram of Fig. 3 SR ⁽⁺⁾ leading edge SR ^(-) trailing edge C _k1 =C ₂₆ =C _k2 =C ₂₈ =0pF 245.7 V/µs 215.4 V/µs C _k1 =C ₂₆ =C _k2 =C ₂₈ =20pF 655.7 V/µs 933.3 V/µs

A further increase in SR and its limit values to 8000-11000 V/μs (see Fig. 8, Fig. 9, Table 2) is ensured in accordance with claim 2 of the invention formula - the introduction of a third 30 additional correction capacitor 30 and an additional current-limiting resistor 31 To reduce overshoot during the front of the transient process, you can change the resistance of this current-limiting resistor 31 (R31=R1).

Table 2 - Dependencies of SR op-amp in the drawing of Fig. 7 from the capacitances of the first 26 (С _к1 =С ₂₆ ), second 28 (С _к2 =С ₂₈ ), and also the third 30 (С _к3 =С ₃₀ ) additional correction capacitors

The capacitances of additional capacitors in the circuit of Fig. 7 SR ⁽⁺⁾ leading edge SR ^(-) trailing edge C _k1 =C ₂₆ =C _k2 =C ₂₈ =20pF, C _k3 =C ₃₀ =0pF 660.4 V/µs 903.2 V/µs C _k1 =C ₂₆ =C _k2 =C ₂₈ =20pF, C _k3 =C ₃₀ =1pF 8000 V/µs 11200 V/µs

From Table 2 it follows that the introduction of a third 30 additional correction capacitor provides a further increase in SR (by more than an order of magnitude) of both the leading and trailing edges of the transient process.

Thus, the claimed device has significant advantages in comparison with the op-amp prototype in terms of the maximum rate of rise of the output voltage.

BIBLIOGRAPHICAL LIST

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Claims (2)

1. A high-speed operational amplifier based on a complementary “bent” cascode, containing the first (1) and second (2) inputs of the device, the first (3) input transistor, the emitter of which is connected to the first (4) power supply bus through the first (5) current-stabilizing two-terminal and connected to the emitter of the second (6) input transistor, the third (7) input transistor, the emitter of which is connected to the second (8) power supply bus through the second (9) current-stabilizing two-terminal network and connected to the emitter of the fourth (10) input transistor, the base of the first (3) and third (7) input transistors are connected to the first (1) input of the device, the bases of the second (6) and fourth (10) input transistors are connected to the second (2) input of the device, the collector of the first (3) input transistor is connected to the second (8) power supply bus through the third (11) current-stabilizing two-terminal network and is connected to the emitter of the first (12) output transistor, the collector of the second (6) input transistor is connected to the second (8) power supply bus through the fourth (13) current-stabilizing two-terminal network and connected to the emitter of the second (14) output transistor, the collector of the third (7) input transistor is connected to the first (4) power supply bus through the fifth (15) current-stabilizing two-terminal network and is connected to the emitter of the third (16) output transistor, the collector of the fourth (10) input transistor is connected with the first (4) power supply bus through the sixth (17) current-stabilizing two-terminal network and connected to the emitter of the fourth (18) output transistor, the collectors of the second (14) and fourth (18) output transistors are connected to the input of the buffer amplifier (19) and the correction capacitor ( 20), the bases of the first (12) and second (14) output transistors are connected to the first (21) bias voltage source, and the bases of the third (16) and fourth (18) output transistors are connected to the second (22) bias voltage source, differing in that that the first (23) and second (24) additional transistors are introduced into the circuit, the emitter of the first (23) additional transistor is connected to the second (8) power supply bus through the parallel-connected first (25) additional current-stabilizing two-terminal network and the first (26) additional correction capacitor, the base of the first (23) additional transistor is connected to the emitter of the first (12) output transistor, the emitter of the second (24) additional transistor is connected to the first (4) power supply bus through the parallel-connected second (27) additional current-stabilizing two-terminal network and the second ( 28) an additional correction capacitor, and the base of the second (24) additional transistor is connected to the emitter of the third (16) output transistor, the collectors of the first (23) and second (24) additional transistors are connected to the input of the buffer amplifier (19), and the collectors of the first (12) ) and third (16) output transistors are connected to the common bus of the first (4) and second (8) power supplies. 2. A high-speed operational amplifier based on a complementary “bent” cascode according to claim 1, characterized in that the combined emitters of the third (7) and fourth (10) input transistors are connected to the combined emitters of the first (3) and second (6) input transistors through third (30) additional correction capacitor and additional current-limiting resistor (31).