RU2802049C1 - Fast differential amplifier - Google Patents

Abstract

FIELD: radio engineering

SUBSTANCE: differential amplifier is proposed, which contains an input stage (1) with current inputs and outputs, the first (7) current source connected between the input node (8) of the input stage (1) and the second (9) bus. The first (10) additional transistor is introduced into the circuit, the base of which is connected to the first (2) input of the input stage (1), the collector is matched with the second (9) bus, and the emitter is connected to the first (6) bus through the first (11) additional source current and is connected to the input node (8) of the input stage (1) through the first (12) additional capacitor, the second (3) input of the device is connected to the base of the second (13) additional transistor, and the collector of the second (13) additional transistor is matched with the second ( 9) bus, the emitter is connected to the first (6) bus through the second (14) additional current source and is connected to the input node (8) of the input stage (1) through the second (15) additional capacitor.

EFFECT: ensuring high levels of output pulse currents.

1 cl, 17 dwg

Description

The invention relates to the field of radio engineering and can be used as a device for amplifying analog signals, in the structure of microcircuits for various functional purposes, for example, in operational amplifiers (op-amps), comparators, current switches of digital-to-analog converters, etc.

Known schemes of classical differential amplifiers (DU) on bipolar [1-8] and field-effect [9-15] transistors, which became the basis of many analog and digital microcircuits. More than 1000 patents in different countries of the world are devoted to the use of this functional unit in specific devices of radio engineering, automation and communication, incl. [1-15].

The closest prototype (Fig. 1) of the claimed device is a differential amplifier, presented in the structure of the Texas Instruments patent US 6.529.076, 2003, which contains an input differential stage 1 with the first 2 and second 3 inputs, the first 4 and second 5 current outputs , consistent with the first 6 power supply bus, the first 7 reference current source connected between the input node 8 of the input differential stage 1, which sets the static mode of its transistors, and the second 9 power supply bus.

A significant drawback of the known control of Fig. 1 is that with large pulse input signals, it has a low speed on the first 4 and second 5 current outputs. This does not allow to perform based on the control of FIG. 1 Various high-speed analog devices such as op amps, comparators, DAC discharge current switches, etc.

The main objective of the proposed invention is to create conditions under which in the PS of Fig. 1 provides high levels of output pulse currents. This increases the rate of recharging parasitic capacitances in the circuit of the first 4 and second 5 current outputs associated with two-terminal loads R _n1 , R _n2 . Ultimately, this effect has a positive effect on the performance of a number of analog devices with the proposed differential amplifier.

The problem is solved by the fact that in the differential amplifier of Fig. 1, containing an input differential stage 1 with the first 2 and second 3 inputs, the first 4 and second 5 current outputs, matched with the first 6 power supply bus, the first 7 reference current source connected between the input node 8 of the input differential stage 1, which sets the static mode of its transistors, and the second 9 power supply bus, new elements and connections are provided - the first 10 additional transistor is introduced into the circuit, the base of which is connected to the first 2 input of the input differential stage 1, the collector is matched with the second 9 power supply bus, and the emitter is connected with the first 6 power supply bus through the first 11 additional reference current source and is connected to the input node 8 of the input differential stage 1, through which the static mode of its transistors is set, through the first 12 additional correction capacitor, the second 3 input of the device is connected to the base of the second 13 additional transistor , and the collector of the second 13 additional transistor is matched with the second 9 power supply bus, the emitter is connected to the first 6 power supply bus through the second 14 additional reference current source and is connected to the input node 8 of the input differential stage 1, which sets the static mode of its transistors, through the second 15 is an additional correction capacitor.

In the drawing of FIG. 1 shows a diagram of the remote control prototype.

In the drawing of FIG. 2 shows a high-speed differential amplifier in accordance with claim 1 of the claims.

In the drawing of FIG. 3 shows a first application example of the fast differential amplifier of FIG. 2 in an operational amplifier based on three current mirrors 20, 21, 22.

In the drawing of FIG. 4 shows the op amp of FIG. 3 with the proposed differential stage in the LTspice environment at t= 27°C, I1= 200µA, R1=1MΩ, I2= I3= 100µA.

In the drawing of FIG. 5 shows the logarithmic amplitude characteristic of the OA (LAFC) of FIG. 4.

In the drawing of FIG. 6 shows on a small scale the transients in the op amp of FIG. 4 in LTspice environment at t= 27°C, I1= 200mkA, R1=1MΩ, I2= I3= 100mkA, Sk=5pF, Vcc= -Vee=5 V and different capacitance values of the first 12 and second 15 additional corrective capacitors (C1 \u003d C2 \u003d 0pF; 5pF; 10pF; 25pF; 50pF).

In the drawing of FIG. 7 is a large scale representation of the transients in the op amp of FIG. 4 (rising edge) in LTspice environment at t= 27°C, I1= 200mkA, R1=1MΩ, I2= I3= 100mkA, Vcc= -Vee=5 V and different capacitance values of the first 12 and second 15 additional corrective capacitors (С1 \u003d C2 \u003d 0pF; 5pF; 10pF; 25pF; 50pF; 100pF; 200pF; 300pF).

In the drawing of FIG. 8 shows on a large scale the transients in the op amp of FIG. 4 (trailing edge) in LTspice environment at t= 27°C, I1= 200mkA, R1=1MΩ, I2= I3= 100mkA, Vcc= -Vee=5 V and different capacitance values of the first 12 and second 15 additional corrective capacitors (C1 \u003d C2 \u003d 0pF; 5pF; 10pF; 25pF; 50pF; 100pF; 200pF; 300pF).

In the drawing of FIG. 9 shows table 1, which shows the numerical values of the maximum slew rate of the output voltage of the op-amp of FIG. 4 at R1=1MΩ, input pulse amplitude 3V, Sk=5pF and different capacitance values of the first 12 and second 15 additional corrective capacitors (C1=C2=0; 5pF; 10pF; 25pF; 50pF).

In the drawing of FIG. 10 shows the second modification of the op-amp with a high-speed differential amplifier of FIG. 2 in LTspice environment at t=27°C, Sk=5pF, I1= 200mkA, Rl=10kOhm, I2= I3= 100mkA, Vcc= -Vee=10V, input pulse signal with amplitude 3V, C1= C2=0pF; 5pF; 10pF; 25pF; 50pF.

In the drawing of FIG. 11 shows the logarithmic frequency response (LAFC) of the OA of FIG. 10.

In the drawing of FIG. 12 shows the transients in the op-amp of Fig.10 (leading edge) in the LTspice environment at t= 27°C, Sk=5pF, I1= 200uA, Rn=10kOhm, I2= I3= 100uA, Vcc= -Vee=10 V and different capacitance values of the first 12 and second 15 additional corrective capacitors (C1= C2=0pF;5pF;10pF;25pF).

In the drawing of FIG. 13 shows transients in the op-amp of FIG. 10 (trailing edge) in LTspice environment at t= 27°C, Sk=5pF, I1= 200uA, Rn=10kΩ, I2= I3= 100uA, Vcc= -Vee=10V and different capacitance values of the first 12 and second 15 additional corrective capacitors (C1 \u003d C2 \u003d 0pF; 5pF; 10pF; 25pF).

In the drawing of FIG. 14 shows table 2, which shows the numerical values of the maximum slew rate of the output voltage of the op-amp of FIG. 10 with load resistance Rn=10kΩ, input pulse amplitude 3V, Sk=5pF and different capacitance values of the first 12 and second 15 additional corrective capacitors (C1=C2=5pF;10pF;25pF).

In the drawing of FIG. 15 shows a third application example of the fast differential amplifier of FIG. 2 in a gallium arsenide op amp. Here the op-amp static mode is shown at I1÷I3 = 200µA, V1 = 6.5V, C1÷C2 = 0pF, _Ck = 3pF, vcc= +10V, vee = -10V.

In the drawing of FIG. 16 shows the logarithmic frequency responses of the open and closed op-amp of FIG. 15.

In the drawing of FIG. 17 shows graphs of the leading edge of the transient process in the op amp of FIG. 15 with an input pulse signal with an amplitude of 3 V and different values of the capacitances of the first 12 and second 15 additional corrective capacitors (C1÷C2 = 0pF, 5pF, 10pF).

The fast differential amplifier of FIG. 2 contains an input differential stage 1 with the first 2 and second 3 inputs, the first 4 and second 5 current outputs, matched with the first 6 power supply bus, the first 7 reference current source connected between the input node 8 of the input differential stage 1, which sets the static the mode of its transistors, and the second 9 bus power supply. The first 10 additional transistor is introduced into the circuit, the base of which is connected to the first 2 input of the input differential stage 1, the collector is matched with the second 9 power supply bus, and the emitter is connected to the first 6 power supply bus through the first 11 additional reference current source and connected to the input node 8 input differential stage 1, which establishes the static mode of its transistors, through the first 12 additional correction capacitor, the second 3 input of the device is connected to the base of the second 13 additional transistor, and the collector of the second 13 additional transistor is matched with the second 9 power supply bus, the emitter is connected to the first 6 power supply bus through the second 14 additional reference current source and is connected to the input node 8 of the input differential stage 1, through which the static mode of its transistors is established, through the second 15 additional corrective capacitor. Two-terminal networks 16 and 17 model the load properties of a differential amplifier (R _n1 , R _n2 ), for example, the second stage of the op-amp, and may have resistive and capacitive components.

In a particular case, the input differential stage 1 can be implemented both on bipolar 18, 19 [1-8] and field-effect [9-15] transistors.

Consider the operation of the control unit of Fig. 2, as well as its influence on the characteristics of operational amplifiers of various modifications.

In static mode, for example, when connecting the first 2 and second 3 remote control inputs of Fig. 2 to a common power supply bus, the static currents of the first 4 and second 5 current outputs are equal to half of the static current of the first 7 reference current source. Due to the rational choice of the currents of the first 11 and second 14 additional reference current sources in the circuit of FIG. 2, it is possible to provide small values of the input current at input 2 and at input 3. If a large pulse signal u _in is applied to the first 2 input, this leads to almost instant blocking of the input differential stage at the second 5 current output and the appearance of a large pulse current through the second 15 an additional correction capacitor, which is transferred to the emitter of the second 13 additional transistor and then closes to the second 9 bus of the power source. In this case, the maximum current of the first 4 current output takes on large values, which ensures fast recharging of the capacitive component of the load 16.

With negative pulse signals at the first 2 input, forcing the process of recharging the capacitive component of the two-terminal load 17 is provided.

Thus, the proposed differential amplifier provides faster recharging of parasitic capacitors in the structure of two-terminal loads 16 and 17.

As input transistors of the input differential stage 1, BJT, CMOS, SOI and other existing modifications of transistors, incl. on wide-gap semiconductors.

Of significant interest is the study of the effectiveness of the proposed differential amplifier Fig. 2 in the structure of several classical operational amplifiers, for example, FIG. 3 (fig.4). In a particular case, the circuit of Fig.3 contains three additional current mirrors 20, 21, 22, a correction capacitor 23 and a buffer amplifier 24, the potential output 25 of which is the output of the op-amp. Computer simulation of the op-amp circuit of Fig. 3 shown in the drawings of FIG. 4, fig. 5, fig. 6 shows that the first 12 and second 15 additional corrective capacitors (C1, C2) in the input differential amplifier significantly reduce the settling time of the transient process in the op-amp and increase the maximum slew rate of its output voltage by more than 300 times (see Fig. 9) .

Computer simulation of the second modification of the OS (Fig.10) with the proposed differential amplifier of Fig. 2 shown in the drawings of FIG. 11, fig. 12, fig. 13 allows us to conclude that the circuit of FIG. 2 increases the speed of the second modification of the op-amp by more than 1000 times (see Fig. 14).

It is important to note that the differential amplifier of FIG. 2 increases the maximum output voltage slew rate for many other op-amp modifications, incl. on the GaAs technological process (Fig. 15, the third modification of the op-amp). Computer simulation of such an op-amp, presented in the graphs of Fig. 16, fig. 17 shows that the introduction of the first 12 and second 15 additional corrective capacitors increases the speed of the gallium arsenide op-amp by more than 40 times.

Thus, the claimed device has significant speed advantages in comparison with the remote control prototype when used in analog circuits, for example, in the structures of operational amplifiers, comparators, voltage stabilizers, etc.

REFERENCES

1. Patent US 3.644.838, fig. 2, 1972 (BJT)

2. Patent US 5.153.529, fig. 1, 1992 (BJT)

3. Patent US 5.610.557, fig. 1, 1997 (BJT)

4. Patent RU 2474953, fig. 2, 2013 (BJT)

5. Patent US 4.600.893, fig. 4, 1986 (BJT)

6. Patent US 6.529.076, 2003 (BJT)

7. Patent US 5.327.100, 1994 (BJT)

8. Patent 4.658.159, fig. 1, 1987 (BJT)

9. Patent US 6.018.268, fig. 1, 1998 (CMOS)

10. Patent US 5.805.021, fig. 26, 1998 (CMOS)

11. US patent 6.304.143, fig. 4, 2001 (CMOS)

12. US Patent 5,734,296, fig. 3, 1998 (CMOS)

13. Patent US 6.580.325, fig. 3, 2003 (CMOS)

14. EP 1083655, fig. 5, 2001 (CMOS)

15. Patent US 8.188.792, fig. 1A, 2012 (CMOS).

Claims (1)

High-speed differential amplifier containing an input differential stage (1) with the first (2) and second (3) inputs, the first (4) and second (5) current outputs, matched with the first (6) power supply bus, the first (7) source reference current, connected between the input node (8) of the input differential stage (1), through which the static mode of its transistors is set, and the second (9) power supply bus, characterized in that the first (10) additional transistor is introduced into the circuit, the base of which connected to the first (2) input of the input differential stage (1), the collector is matched to the second (9) power supply bus, and the emitter is connected to the first (6) power supply bus through the first (11) additional reference current source and connected to the input node (8) of the input differential stage (1), through which the static mode of its transistors is set, through the first (12) additional corrective capacitor, the second (3) input of the device is connected to the base of the second (13) additional transistor, and the collector of the second (13) additional transistor is matched with the second (9) power supply bus, the emitter is connected to the first (6) power supply bus through the second (14) additional reference current source and is connected to the input node (8) of the input differential stage (1), which sets the static mode its transistors, through the second (15) additional corrective capacitor.