CN210327524U - Single-pole double-throw switch circuit of TypeC interface, analog switch chip and electronic equipment - Google Patents
Single-pole double-throw switch circuit of TypeC interface, analog switch chip and electronic equipment Download PDFInfo
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Abstract
The utility model provides a single-pole double-throw switch circuit, analog switch chip and electronic equipment of TypeC interface can produce reverse bias voltage at first diode both ends, because after the PN junction adds a reverse bias voltage, can make the capacitance value of this PN junction can show and reduce. Furthermore, the capacitance to ground at the COM point when the first field effect transistor, namely the audio channel, is turned off can be effectively reduced, so that the bandwidth of the digital channel is prevented from being reduced due to the overlarge capacitance. It is thus clear, based on the utility model discloses, can be convenient for realize the jumbo size of first field effect transistor and the high bandwidth of digital access simultaneously to can be convenient for promote the THD performance of analog audio access and the bandwidth of digital access simultaneously, avoid the conflict between the two.
Description
Technical Field
The invention relates to electronic equipment, in particular to a single-pole double-throw switch circuit of a TypeC interface, an analog switch chip and electronic equipment.
Background
For electronic products supporting a type c interface, a special analog switch chip containing two paths of single-pole double-throw switch circuits is often needed, wherein a high-speed USB digital signal and an analog audio signal can be output in a time-sharing manner through a D + pin and a D-pin in the type c interface.
In order to be suitable for outputting high-speed USB digital signals and analog audio signals in a time-sharing mode, a digital path for outputting the USB digital signals and an analog audio path for outputting the analog audio signals can be arranged in the circuit.
In the related art, high-speed USB digital signal transmission in the digital channel needs to support high bandwidth, and analog audio signal transmission in the analog audio channel needs to support very small total harmonic distortion. These two requirements can conflict in the analog audio path, for example:
in order to ensure good THD performance of the audio of the analog audio path, it is necessary to increase the size of the fet constituting the analog audio path as much as possible, however, if the size of the fet in the analog audio path is increased, the off capacitance when the analog audio path is turned off becomes large, and the digital path bandwidth becomes small due to the excessively large off capacitance when the analog audio path is turned off.
Therefore, in the prior art, it is difficult to consider the THD performance of the audio of the analog audio path and the bandwidth of the digital path.
Disclosure of Invention
The invention provides a single-pole double-throw switch circuit of a TypeC interface, an analog switch chip and electronic equipment, and aims to solve the problem that the THD performance of audio of an analog audio channel and the bandwidth of a digital channel are difficult to be considered simultaneously.
According to a first aspect of the present invention, there is provided a single-pole double-throw switch circuit of a TypeC interface, comprising: the device comprises a digital channel and an analog audio channel which can be conducted in a time-sharing mode and are connected to the same COM port, wherein two pins of the COM port are respectively connected to a D + pin and a D-pin of a TypeC interface; the analog audio channel is provided with a first field effect transistor, and a PN junction between a substrate and a source electrode of the first field effect transistor can form a first diode; the substrate of the first field effect transistor is a first end of the first diode, and the source electrode of the first field effect transistor is a second end of the first diode;
the circuit, still include: a reverse bias voltage module;
the reverse bias voltage module is connected between the first diodes and used for generating reverse bias voltage at two ends of the first diodes.
Optionally, the reverse bias voltage module includes an isolation field effect transistor, a voltage adjusting unit, and an impedance unit capable of generating a voltage drop when a current flows through the isolation field effect transistor, a drain of the isolation field effect transistor is connected to the target circuit, and a source of the isolation field effect transistor is connected to one end of the impedance unit;
the grid electrode of the field effect tube for isolation and the second end of the first diode are connected to a first node in common; the other end of the impedance unit and the first end of the first diode are connected to a second node in common;
when the reverse bias voltage is generated, the potential of the first node is higher than that of the second node, and the voltage between the first node and the second node is the reverse bias voltage;
the voltage adjusting unit is connected to the second node and is configured to adjust the reverse bias voltage so that the reverse bias voltage is within a required value range or a required value.
Optionally, the voltage regulating unit includes a current determining device connected to the second node;
the current determination device is used for determining the current magnitude of the second node, so that the reverse bias voltage can be in a required value range or a required value.
Optionally, the current determining device comprises a current source connected to the second node.
Optionally, the impedance unit includes a resistor connected in series between the source of the isolation fet and the second node.
Optionally, the second node is further connected to a third node, a potential of the third node is lower than that of the second node, the voltage adjustment unit includes a variable voltage source disposed between the second node and the third node, and the variable voltage source is configured to determine a voltage between the third node and the second node, so that the reverse bias voltage can be within a required value range or a required value.
Optionally, the voltage value of the reverse bias voltage ranges from 4 volts to 5 volts.
Optionally, the digital path is provided with a second field effect transistor, and a PN junction between a substrate and a source of the second field effect transistor can form a second diode.
According to a second aspect of the invention, there is provided an analog switch chip comprising a two-way first aspect and a single pole double throw switch circuit of the TypeC interface according to the alternative.
According to a third aspect of the present invention, there is provided an electronic device including the analog switch chip relating to the second aspect and the alternatives thereof.
The single-pole double-throw switch circuit, the analog switch chip and the electronic equipment of the TypeC interface provided by the invention can generate reverse bias voltage at two ends of the first diode, and the capacitance value of the PN junction can be obviously reduced after the reverse bias voltage is added to the PN junction. Furthermore, the capacitance to ground at the COM point when the first field effect transistor, namely the audio channel, is turned off can be effectively reduced, so that the bandwidth of the digital channel is prevented from being reduced due to the overlarge capacitance. Therefore, based on the invention, the large size of the first field effect transistor and the high bandwidth of the digital channel can be realized conveniently, so that the THD performance of the analog audio channel and the bandwidth of the digital channel can be improved conveniently, and the conflict between the two can be avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a first schematic diagram illustrating a configuration of a single-pole double-throw switch circuit of a TypeC interface according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of one voltage-capacitance characteristic of a PN junction at a reverse bias voltage;
FIG. 3 is a second schematic diagram of a single-pole double-throw switch circuit of the TypeC interface according to an embodiment of the present invention;
FIG. 4 is a third schematic diagram of a single-pole double-throw switch circuit of the TypeC interface according to an embodiment of the present invention;
FIG. 5 is a circuit diagram of a single-pole double-throw switch circuit of the TypeC interface according to an embodiment of the invention.
Description of reference numerals:
1. n1-first field effect transistor;
2. n2-second field effect transistor;
3. d1 — first diode;
4-reverse bias voltage module;
41. n3-field effect tube for isolation;
42-impedance unit;
r-resistance;
43-a voltage regulation unit;
431-a current determining device;
4311-Current Source;
a 5-COM port;
6-a first node;
7-a second node;
8-a third node;
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Fig. 1 is a first schematic diagram of a configuration of a single-pole double-throw switch circuit of a TypeC interface according to an embodiment of the present invention.
Referring to fig. 1, the single-pole double-throw switch circuit of TypeC interface includes: the COM interface circuit can be conducted in a time-sharing mode, and is connected to a digital channel and an analog audio channel of the same COM port 5, and two pins of the COM port 5 are respectively connected to a D + pin and a D-pin of a TypeC interface.
An analog audio path is understood to mean a path for transmitting an analog audio signal, which path is formed by the components and the connecting line.
In this embodiment, the analog audio channel is provided with a first field effect transistor 1, and a PN junction between a substrate and a source of the first field effect transistor 1 can form a first diode 3; the substrate of the first field effect transistor 1 is a first end of the first diode 3, and the source of the first field effect transistor 1 is a second end of the first diode 3.
Specific examples thereof include: in the structure of the field effect transistor, two N regions can be formed on a P-type silicon wafer substrate and are respectively used as a source region and a drain region and connected with corresponding electrodes, wherein a PN junction exists between the substrate and a single N region, and then the PN junction can form the first diode related to the above and the second diode related to the later.
Further, any path for transmitting an analog audio signal having the first field effect transistor 1 can be understood as an analog audio path according to the present embodiment.
A digital path is understood to be a path for transmitting high-speed USB digital signals, which is formed by the devices and the connecting lines.
In one embodiment, the digital path is provided with a second field effect transistor, and further, a PN junction between the substrate and the source of the second field effect transistor 2 can form a second diode. The relationship between the second fet and the second diode can be understood by referring to the relationship between the first fet and the first diode.
Referring to fig. 1, in the present embodiment, the circuit further includes: a reverse bias voltage module 4; the reverse bias voltage module 4 is connected to two ends of the first diode 3, and is configured to generate a reverse bias voltage across the first diode 3. Further, the reverse bias voltage module 4 generates a reverse bias voltage at the substrate and the source of the first fet 1.
The voltage value of the reverse bias voltage can be configured or changed at will according to requirements. In a specific implementation process, the voltage value can range from 4 volts to 5 volts. It is to be understood that the present invention is not limited to the above-described embodiments, but may be implemented in other embodiments.
The circuit structure of the reverse bias voltage module 4 referred to above may be various, and any circuit module that can generate a reverse bias voltage does not depart from the description of the present embodiment.
Fig. 2 is a voltage-capacitance characteristic diagram of a PN junction at a reverse bias voltage.
Referring to fig. 2, the horizontal axis represents the voltage of the PN junction in volts, which can be characterized by V, and the vertical axis represents the capacitance of the off-state capacitor of the PN junction in picofarads, which can be characterized by pF.
The PN junction can be understood as: p-type and N-type semiconductors are fabricated on the same semiconductor substrate, and a space charge region called PN junction is formed by the interface
The off-capacitance is understood to be a capacitance Coff to ground corresponding to the COM point (i.e. the second end of the first diode) when the fet of the audio channel is turned off. As shown in fig. 2, after applying a reverse bias voltage to the PN junction, the capacitance of the PN junction is significantly reduced, thereby significantly reducing the capacitance Coff to ground at the COM point.
Therefore, the embodiment can effectively reduce the capacitance to ground at the COM point when the first field effect transistor is turned off, thereby avoiding the bandwidth of the digital path from becoming smaller due to the overlarge capacitance. Therefore, based on the invention, the large size of the first field effect transistor and the high bandwidth of the digital channel can be realized conveniently, so that the THD performance of the analog audio channel and the bandwidth of the digital channel can be improved conveniently, and the conflict between the two can be avoided.
Based on the idea related to the embodiment, the method can help related personnel to make products which are better than the product performance on the market at present.
Fig. 3 is a schematic structural diagram of a single-pole double-throw switch circuit of a TypeC interface according to an embodiment of the present invention.
Referring to fig. 3, the reverse bias voltage module includes an isolation fet 41, a voltage regulator 43, and an impedance unit 42 capable of generating a voltage drop when a current flows through the isolation fet, a drain of the isolation fet 41 is connected to a target circuit (not shown, which may be any other circuit except a single-pole double-throw switch circuit of a TypeC interface in a chip), and a source of the isolation fet 41 is connected to one end of the impedance unit 42.
The gate of the isolation fet 41 and the second terminal of the first diode 3 (or the source of the first fet 1) are connected in common to a first node 6; the other end of the impedance unit 42 is connected in common with the first end of the first diode 3 (or the substrate characterized by the first field effect transistor 1) to a second node 7.
The first node and the second node, and the third node referred to hereinafter, may be understood as: when a circuit is represented as a circuit diagram, the same circuit positions in an actual circuit or different circuit positions which are connected with each other and have the same potential can be represented as the same node due to the same potential, and the circuit positions which have the same potential and are connected can be represented uniformly through the description mode of the node in the above embodiment mode, so that the connection relation and the action principle of the circuit can be more clearly represented.
It can also be understood as: the first node refers to any circuit position respectively connected to the gate of the isolation fet 41 and the second terminal of the first diode 3 (or characterized as the source of the first fet 1) and thus having the same potential as the gate; the first node refers to any circuit location connected to the other end of the impedance unit 42 and the first end of the first diode 3 (or the substrate characterized by the first field effect transistor 1), and thus having the same potential as the other end.
Therefore, the nodes related to this embodiment and its alternatives may not refer to a pin, a terminal, a device, etc. connected to any one of them. Meanwhile, the present embodiment does not exclude the case where the node is a certain pin, terminal, or device.
When the reverse bias voltage is generated, the potential of the first node 6 is higher than the potential of the second node 7, and the voltage between the first node 6 and the second node 7 is the reverse bias voltage.
The voltage adjusting unit 43 is connected to the second node 7, and is configured to adjust the reverse bias voltage, so that the reverse bias voltage is within a required value range or a required value.
Specifically, if the current value of the current flowing through the impedance unit 42 is represented by I, the resistance value of the impedance generated by the impedance unit 42 is represented by R, and the voltage value of the voltage between the gate and the source of the isolation fet 41 can be represented by Vgs, which is usually a fixed value, then: the voltage value Vx of the reverse bias voltage generated when the isolation fet 41 is turned on can be determined by the following equation: vx is Vgs + I R.
Further, in the above embodiment, by selecting the impedance unit 42 having different resistance values, different reverse bias voltages can be realized, thereby satisfying various demands.
In one example, the impedance unit 42 may include a resistor connected in series between the source of the isolation fet 41 and the second node 7, for example, one or more resistors, and if a plurality of resistors are included, the impedance unit 42 may be determined by connecting the plurality of resistors in series and/or in parallel.
In other examples, the impedance unit 42 may also include a zener diode, and/or: other elements that can generate impedance.
In addition to the impedance unit 42 and the isolation fet 41, the reverse bias voltage can be adjusted by changing the current flowing through the impedance unit 42, thereby further satisfying various requirements.
Fig. 4 is a schematic structural diagram three of a single-pole double-throw switch circuit of a TypeC interface according to an embodiment of the present invention.
Referring to fig. 4, the voltage regulating unit 43 includes a current determining device 431 connected to the second node 7, wherein: the second node 7 is further connected to a third node 8, the potential of the third node 8 is smaller than the potential of the second node 7, and a current determining device 431 is provided between the second node 7 and the third node 8.
The current determining device 431 may be understood as any circuit structure for determining the current magnitude of the second node 7 so that the reverse bias voltage can be within a desired value range or a desired value. When the current of the second node 7 changes, the current of the impedance unit 42 may also change, and in a specific implementation, the current of the second node 7 may be the same as or similar to the current flowing through the impedance unit 42.
In one example, the current determining device 431 includes a current source connected to the second node 7, which may be a current source 4311 shown in fig. 5.
By changing the current magnitude in the current power supply, for example, adjusting the current value of the current source, the reverse bias voltage can be adjusted conveniently, and the requirement is further met.
In other alternative embodiments, instead of using the current unit 43, the second node 7 may be connected to a variable voltage source, in addition to the embodiments described above. For example: the voltage adjusting unit 43 includes a variable voltage source disposed between the second node and the third node, and the variable voltage source is configured to determine a voltage between the third node and the second node, so that the reverse bias voltage can be within a required value range or a required value. The variable voltage source may maintain a fixed voltage difference between the voltages of the second node 8 and the first node 6.
In the above embodiment, the isolation of the new current source and the related circuit from the COM port can be realized by the isolation fet 41.
FIG. 5 is a circuit diagram of a single-pole double-throw switch circuit of the TypeC interface according to an embodiment of the invention.
Referring to fig. 5, wherein the first fet is characterized by N1, the second fet by N2, the isolation fet by N3, and the first diode by D1, for ease of understanding, the first diode D1 is specifically illustrated in fig. 5, which is actually a PN junction between the source and the substrate of the first fet N1. Meanwhile, the a node, the B node, the C node, the D node and the E node may be further characterized, wherein the C node may be understood as the first node, the D node may be understood as the second node, and the E node may be understood as the third node.
Further, the path between the a node and the C node may be enumerated as a digital path, and the path between the B node and the C node may be enumerated as an analog audio path.
The increased reverse bias voltage can enable the turn-off capacitance corresponding to the node C to be obviously reduced, and further the signal bandwidth from the COM port 5 to the node A can be conveniently improved.
At the same time, the size of the first fet 1 may be increased to improve the THD performance of the COM port to node B analog signal, while the reverse bias voltage across the first diode D1 may be increased to maintain the off capacitance not increased or still slightly decreased to ensure that the COM port to node a signal bandwidth is not affected.
In the specific implementation process, through the implementation of the alternative embodiment, the off-state capacitance can be greatly reduced from about 4pF to about 1pF, so that the performance parameter of the switch is greatly improved.
The THD referred to above may specifically be: total Harmonic discrimination, which can be described as: the total harmonic distortion can be characterized by using the ratio of the root mean square of various harmonic components of the output signal to the input signal, and the THD has a great correlation with the performance of the audio, so that the improvement of the total harmonic distortion can effectively improve the performance of the audio.
The Bandwidth referred to above may be characterized as BW, in particular Bandwidth, and may be characterized by the difference between the highest frequency and the lowest frequency of the signal of a certain signal path, for example.
The embodiment also provides an analog switch chip which comprises a single-pole double-throw switch circuit of the TypeC interface related to more than two alternatives.
The present embodiment also provides an electronic device including the analog switch chip to which the above alternative relates.
In summary, the single-pole double-throw switch circuit, the analog switch chip, and the electronic device of the TypeC interface provided in this embodiment can generate a reverse bias voltage at two ends of the first diode, and after a reverse bias voltage is applied to the PN junction, the capacitance of the PN junction can be significantly reduced. Furthermore, the capacitance to ground at the COM point when the first field effect transistor, namely the audio channel, is turned off can be effectively reduced, so that the bandwidth of the digital channel is prevented from being reduced due to the overlarge capacitance. Therefore, based on the invention, the large size of the first field effect transistor and the high bandwidth of the digital channel can be realized conveniently, so that the THD performance of the analog audio channel and the bandwidth of the digital channel can be improved conveniently, and the conflict between the two can be avoided.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A single pole, double throw switching circuit for a TypeC interface comprising: the device comprises a digital channel and an analog audio channel which can be conducted in a time-sharing mode and are connected to the same COM port, wherein two pins of the COM port are respectively connected to a D + pin and a D-pin of a TypeC interface; the analog audio channel is provided with a first field effect transistor, and a PN junction between a substrate and a source electrode of the first field effect transistor can form a first diode; wherein, the substrate of first field effect transistor is the first end of first diode, the source electrode of first field effect transistor is the second end of first diode, its characterized in that still includes: a reverse bias voltage module;
the reverse bias voltage module is connected between the first diodes and used for generating reverse bias voltage at two ends of the first diodes.
2. The circuit of claim 1, wherein the reverse bias voltage module comprises an isolation field effect transistor, a voltage regulating unit, and an impedance unit capable of generating a voltage drop when a current flows through the isolation field effect transistor, wherein a drain of the isolation field effect transistor is connected to a target circuit, and a source of the isolation field effect transistor is connected to one end of the impedance unit;
the grid electrode of the field effect tube for isolation and the second end of the first diode are connected to a first node in common; the other end of the impedance unit and the first end of the first diode are connected to a second node in common;
when the reverse bias voltage is generated, the potential of the first node is higher than that of the second node, and the voltage between the first node and the second node is the reverse bias voltage;
the voltage adjusting unit is connected to the second node and is configured to adjust the reverse bias voltage so that the reverse bias voltage is within a required value range or a required value.
3. The circuit of claim 2, wherein the voltage regulating unit includes a current determining device connected to the second node;
the current determination device is used for determining the current magnitude of the second node, so that the reverse bias voltage can be in a required value range or a required value.
4. The circuit of claim 3, wherein the current determining device comprises a current source connected to the second node.
5. The circuit of claim 2, wherein the impedance unit comprises a resistor connected in series between the source of the isolation fet and the second node.
6. The circuit of claim 2, wherein the second node is further connected to a third node, the third node has a lower potential than the second node, and the voltage adjustment unit comprises a variable voltage source disposed between the second node and the third node, and the variable voltage source is configured to determine a voltage between the third node and the second node, so that the reverse bias voltage can be within a desired value range or a desired value.
7. The circuit of any of claims 1-6, wherein the reverse bias voltage has a value in a range of 4 volts to 5 volts.
8. The circuit according to any of claims 1 to 6, wherein the digital path is provided with a second field effect transistor, the PN junction between the substrate and the source of which is capable of forming a second diode.
9. An analog switch chip comprising two single-pole double-throw switch circuits of the TypeC interface of any one of claims 1 to 8.
10. An electronic device comprising the analog switch chip of claim 9.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921419678.8U CN210327524U (en) | 2019-08-28 | 2019-08-28 | Single-pole double-throw switch circuit of TypeC interface, analog switch chip and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921419678.8U CN210327524U (en) | 2019-08-28 | 2019-08-28 | Single-pole double-throw switch circuit of TypeC interface, analog switch chip and electronic equipment |
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| CN210327524U true CN210327524U (en) | 2020-04-14 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110365323A (en) * | 2019-08-28 | 2019-10-22 | 上海爻火微电子有限公司 | Single-pole double-throw switch (SPDT) circuit, analog switch chip and the electronic equipment of TypeC interface |
-
2019
- 2019-08-28 CN CN201921419678.8U patent/CN210327524U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110365323A (en) * | 2019-08-28 | 2019-10-22 | 上海爻火微电子有限公司 | Single-pole double-throw switch (SPDT) circuit, analog switch chip and the electronic equipment of TypeC interface |
| CN110365323B (en) * | 2019-08-28 | 2024-06-07 | 上海爻火微电子有限公司 | Single-pole double-throw switch circuit of TypeC interface, analog switch chip and electronic equipment |
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Granted publication date: 20200414 Effective date of abandoning: 20240607 |