RU2785218C1 - METHOD FOR ADAPTIVE MAJORIZATION OF ELEMENTS “n OR MORE of (2n-1)” - Google Patents

Abstract

FIELD: computer technology.

SUBSTANCE: technical solution relates to the field of computer technology. The expected result is achieved due to the method for adaptive majorization of elements, which consists in the fact that a fault-tolerant computing system is formed in the system, containing a group of central processors, the output information from the outputs of which is majorized in one of the ways: 2 out of 3, 3 or more out of 5, 4 or more out of 7 or 5 or more out of 9, etc., and adaptive majorization in the system is performed by summing all (2n-1) majorized binary signals; the result of summing all (2n-1) majorized binary signals is compared with the value of n; after that, the result of comparing the output of the adder with the value of n is taken as the value of the majorization result.

EFFECT: elimination of temporary redundancy for the analysis and search for a faulty channel, as well as for the programmatic transition to the lower version of majorization due to adaptive majorization of elements “n or more of (2n-1)”.

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Description

The invention relates to automation and computer technology and can be used for continuous monitoring of the operability of computer equipment operating in conditions of continuous dynamics and constant changes in the parameters of external conditions and taking into account increased requirements for their reliability.

There is a known method of majority voting in a computer system [1]. According to the well-known method of majority voting in a computing system, a fault-tolerant computing system is formed containing a group of central processors, the output information from the outputs of which is dominated in one of the following ways: 2 out of 3, 3 or more out of 5, 4 or more out of 7 or 5 or more out of 9, etc. .d. The choice of the majority voting option and the transition from one option in the system is carried out programmatically.

The disadvantage of this method is the need for temporary redundancy for the analysis and search for a faulty channel, as well as for a software transition to the lower version of the majority.

The closest to the proposed solution is the method of majorityization in the computing system [1], according to which a fault-tolerant computing system is formed in the computing system, containing a group of central processors, the output information from the outputs of which is dominated by one of the following methods: 2 out of 3, 3 or more out of 5, 4 or more out of 7 or 5 or more out of 9, etc.

By a known method of majority voting in a computing system, a fault-tolerant computing system is formed containing a group of central processors, the output information from the outputs of which is dominated in one of the following ways: 2 out of 3, 3 or more out of 5, 4 or more out of 7 or 5 or more out of 9, etc. d.

The technical result of the invention is a method for adaptive majority voting of elements "n and more from (2n-1)", where n=1,2, 3, etc.

The technical result is achieved by the fact that in the method in which adaptive majority voting in the system is performed by summing all (2n-1) majority binary signals. The result of the summation of all (2n-1) majority binary signals is compared with the value of n, after which the result of comparing the output of the adder with the value of n is taken as the value of the result of the majority.

The drawing shows a block diagram (see Fig. 1) majority (2n-1) binary signals. The drawing shows:

1) combination type adder (1);

2) delay element (2);

3) a register for storing the number n (3);

4) comparison scheme (4);

5) block for analyzing faulty channels (5);

6) inputs of majority (2n-1) binary signals (6);

7) clock signal input (7);

8) output dominated binary signal (8);

9) numbers of faulty channels (9).

Majority signals X _i (i=1,2,…(2n-1)) are fed to the inputs of the adder 1, where they are added according to the timing signal from input 7. The result from the output of adder 1 is fed to the first input of the comparison circuit 4, the second input of which receives the code of the number n from the output of register 3. Element 2 delays the clock signal for the time of reliable operation of the adder 1. The result of the majority will be equal to 1 if the value of the code at the output of the adder will be greater than or equal to n, and 0 otherwise. In addition, the signal from the output of the comparison circuit 4 is fed to the block 5 of the analysis of faulty channels.

The method includes the following operations:

1. Adaptive majority voting in the system is performed by summing all (2n-1) majority binary signals.

2. The result of the summation of all (2n-1) majority binary signals is compared with the value n.

3. The result of comparing the output of the adder with the value of n is taken as the value of the result of the majority.

The method of adaptive majority voting in the system makes it possible to carry out continuous monitoring of the operability of computer equipment operating under conditions of continuous dynamics and constant changes in the parameters of external conditions and taking into account increased requirements for their reliability.

Thus, this method of adaptive majority voting in the system is performed by summing any of all (2n-1) majority binary signals, while the result of comparing the output of the adder with the value of the number n is taken as the value of the result of majority voting.

1. RU No. 2716061, class. G06F 7/57, H03K 19/23, 2019.

Claims (1)

The method of adaptive element majoritation, which consists in the fact that a fault-tolerant computing system is formed in the system, containing a group of central processors, the output information from the outputs of which is dominated in one of the following ways: 2 out of 3, 3 or more out of 5, 4 or more out of 7 or 5, and more than 9, etc., characterized in that the adaptive majority voting in the system is performed by summing all (2n-1) majority binary signals; the result of the summation of all (2n-1) majority binary signals is compared with the value n; after that, the result of comparing the output of the adder with the value n is taken as the value of the result of the majority.

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