RU2818031C1 - Adaptive majority block of elements "n and more of (2n-1)" - Google Patents

Abstract

FIELD: computer engineering.

SUBSTANCE: invention relates to automation and computer engineering and can be used for continuous monitoring of computer equipment operability, operating in conditions of continuous dynamics and constant changes of parameters of external conditions and taking into account increased requirements to their reliability. Device comprises a group of OR elements, a group of AND elements, a group of mod 2 addition elements, a counter, a group of triggers, a group of delay elements, a group of differentiating chains.

EFFECT: higher survivability and fault tolerance of the computer system due to multiple redundancy of information processing channels and subsequent adaptive majorization of output data of all data processing channels.

1 cl, 1 dwg, 1 tbl

Description

The invention relates to automation and computer technology and can be used for continuous monitoring of the performance of computer equipment operating under conditions of continuous dynamics and constant changes in the parameters of external conditions and taking into account increased requirements for their reliability.

The technical result is to increase the survivability and fault tolerance of the computing system.

The proposed device is based on multiple redundancy of information processing channels in a computer system and subsequent adaptive majoritization of the output data of all data processing channels. Hardware redundancy is managed depending on the state of the computing system in hardware.

The closest in technical essence is the majority block of elements, for example, [1]. According to known majority devices in a computing system, a fault-tolerant computing system is formed, containing a group of central processors, the output information from the outputs of which is majorityized in one of the following ways: 2 out of 3, 3 or more out of 5, 4 or more out of 7 or 5 or more out of 9, etc. e. The selection of a majority option and the transition from one option to another option in the system is carried out programmatically.

The disadvantage of the known majoritization device [1] is the need for temporary redundancy for analysis and search for a faulty channel, as well as for a software transition to the lower majoritization level.

According to the proposed block, adaptive majoritization in a computing system is performed by forcibly sending a zero to the output of the first (odd number) failed channel of the computing system and forcing one to the output of the second (even number) failed channel of the computing system, thereby reducing in hardware only the level of majoritization in computing system, while the reliable operation of the computing system is maintained up to two serviceable channels in the computing system.

The purpose of the proposed block is to increase the reliability, survivability and fault tolerance of the computing system.

This goal is achieved by the fact that in an adaptive majority block containing a group of first OR elements (1 ₁ , ... 1 _n ), a group of mod 2 addition elements (2 ₁ , ... 2 _n ), a group of first triggers (3 ₁ , ... 3 _n ), a group of first AND elements (5 ₁ , ... 5 _n ), the first OR element (8), a counter (10), a block (11) of majority elements “n or more of (2n-1)”, ( as an example “ 3 out of 5 "), second AND element (13), second OR element (14), third AND element (15), third OR element (16), fourth OR element (17), fourth AND element (18), fifth element AND (19), the fifth OR element (20), the sixth OR element (21), the sixth AND element (12), the inputs (24 ₁ , ... 24 _n ) of the block are connected to the first inputs of the same name of the first OR elements (1 ₁ , ... 1 _n ), the output of the first OR element (1 ₁ ) is connected to the first input of the third AND element (15) and to the first input of the third OR element (16), the output of the second OR element (1 ₂ ) is connected to the second input of the third AND element (15) and to the second input of the third OR element (16), the output of the third OR element (1 ₃ ) is connected to the first input of the second AND element (13) and to the first input of the second OR element (14), the output of the fourth OR element (1 ₄ ) is connected to the second input of the second AND element (13) and to the second input of the second OR element (14), the output of the fifth OR element (1 ₅ ) is connected to the first input of the sixth OR element (21), the output of the second AND element (13) is connected to the first input of the fourth OR element (17), the output of the second OR element (14) is connected to the first input of the fourth AND element (18), the output of the third AND element (15) is connected to the second input of the fourth OR element (17), the output of the third OR element (16) is connected to the second input of the fourth AND element (18), the output of which is connected to the first input of the fifth AND element (19) and to the first input of the fifth OR element (20), the output of the fourth OR element (17) is connected to the second input of the fifth AND element (19) and to the second input of the fifth OR element (20), the output of the fifth AND element (19) is connected to the second input of the sixth OR element (21), the output of which is connected to the first input of the sixth AND element (12), the output of the fifth OR element (20) is connected to the second input of the sixth element AND (12), the output of which is the output of device 22, a group of second triggers (4 ₁ , ... 4 _n ), a group of delay elements (6 ₁ , ... 6 _n ), a group of differentiating chains (7 ₁ , ... 7 _n ), a trigger with a counting input (9), the outputs of the first OR elements (1 ₁ , ... 1 _n ) are connected to the first inputs of the same addition elements mod 2 (2 ₁ , ... 2 _n ), the outputs of which are connected to the first inputs of the same the first triggers (3 ₁ , … 3 _n ), the outputs of which are connected to the inputs of the delay elements of the same name (6 ₁ , … 6 _n ) and differentiating chains (7 ₁ , … 7 _n ), the outputs of the differentiating chains (7 ₁ , … 7 _n ) connected to the same inputs of the first OR element (8), the output of which is connected to the input of the counter (10) and to the input of the trigger with a counting input (9), the output of which is connected to the first inputs of the first AND elements (5 ₁ , ... 5 _n ), the second whose inputs are connected to the outputs of the delay elements of the same name (6 ₁ , ... 6 _n ), the outputs of the first AND elements (5 ₁ , ... 5 _n ) are connected to the inputs of the second flip-flops of the same name (4 ₁ , ... 4 _n ), the outputs of which are connected to the second inputs namesake first triggers (3 ₁ , … 3 _n ) and to the second inputs of the first OR elements (1 ₁ , … 1 _n ), the output of the sixth AND element (12) is connected to the second inputs of the addition elements mod 2 (2 ₁ , … 2 _n ),

A search in the known scientific and technical literature did not reveal the presence of such technical solutions.

The essence of the invention illustrated by drawing. In fig. Figure 1 shows a schematic representation of the adaptive majority block of elements “nand more from(2n -1)"

The essence of the invention is illustrated by the drawing. The adaptive majority block of elements “ n or more of (2n -1) ” (Fig. 1) contains: a group of elements OR (1 ₁ , ... 1 _n ), a group of addition elements mod 2 (2 ₁ , ... 2 _n ), a group triggers (3 ₁ , … 3 _n ), trigger group (4 ₁ , … 4 _n ), group of AND elements (5 ₁ , … 5 _n ), delay elements group (6 ₁ , … 6 _n ), group of differentiating chains (7 ₁ , ... 7 _n ), OR element (8), trigger with counting input (9), counter (10), block of majority elements (11) (using the example of the block of elements “ 3 of 5 ”), AND element (12), AND element (13), OR element (14), AND element (15), OR element (16), OR element (17), AND element (18), AND element (19), OR element (20), OR element (21), element AND (22), outputs (22, 23), inputs (24 ₁ , ... 24 _n ) together with connections.

The block works as follows. In the initial state, all flip-flops (3 ₁ , ... 3 _n ), flip-flops (4 ₁ , ... 4 _n ), a flip-flop with a counting input (9), and a counter (10) are in the zero state.

Elements 12 – 21 implement the function F of the majority body (hereinafter, block “3 of 5” is considered as an example) in accordance with Table 1.

Table 1

N 1 2 3 4 5 F 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1

If one of the five channels fails (for example, the first, that is, x ₁ =0 , and x ₂ =x ₃ =x ₄ =x ₅ =1 ), the output 22 of the majority block 11 will have a single signal, which is supplied to the first inputs all elements of addition mod 2 (2 ₁ , ... 2 ₅ ). At the output of the OR element 1 ₁ there will be a zero signal, which is fed to the second input of the addition element mod 2 (2 ₁ ), from the output of which a single signal sets the trigger (3 ₁ ) to the single state.

A single signal from the output of the trigger (3 ₁ ) through the differentiating chain (7 ₁ ) and the OR element (8) sets the counter (10) and the trigger with the counting input (9) to a single state, after which at the first input of the AND element (5 ₁ ) there will be a single signal. The delay element (6 ₁ ) delays the signal for the time of reliable operation of the differentiating chain (7 ₁ ), the OR element (8) and the trigger with a counting input (9).

A single signal from the output of element AND 5 ₁ sets trigger 4 ₁ to a single state. A single signal from the output of trigger 4 ₁ resets trigger 3 ₁ to the zero state, and the output of OR element 1 ₁ will now have a single signal, that is, further x ₁ =1 .

Further, in the event of a possible failure of one more channel (for example, the fifth, that is x ₅ =0 , and x ₁ =x ₂ =x ₃ =x ₄ =1 ) at the output of the majority body (11) (output of element I (12 )) there will be a single signal, which is fed to the second inputs of all addition elements mod 2 (2 ₁ , ... 2 ₅ ). At the output of the OR element (1 ₅ ), there will be a zero signal, which is fed to the first input of the addition element mod 2 (2 ₅ ), from the output of which a single signal sets the trigger (3 ₅ ) to the single state.

A single signal from the output of the trigger (3 ₅ ) through the differentiating chain (7 ₅ ) and the OR element (8) sets the trigger with the counting input (9) now to the zero state, after which there will be a zero signal at the second input of the AND element (5 ₅ ). A zero signal from the output of the AND element (5 ₅ ) will not set the trigger (4 ₅ ) to the single state. The zero signal from the trigger output (4 ₅ ) is supplied to the second input of the OR element (1 ₅ ), so the output of the OR element (1 ₅ ) will be a zero signal, that is, x ₅ =0 .

The code for the number of failures in the system from the output of the counter (10) is supplied to the output (23) of the device.

Thus, if two of the five channels fail sequentially, the majority block of elements “3 or more out of 5” will work properly. However, a zero signal will be sent to one faulty input of the majority block of elements “n or more of (2n-1)” , and a single signal will be sent to the second faulty input, the original adaptive majority block of elements “n or more of (2n-1) )” the majority block of elements is automatically rebuilt into the system one step lower in rank, which significantly increases the reliability of the information processed by the majority block.

1. AS No. 2716061, class. G06F 12/14, 2020.

Claims (1)

Adaptive majority block of elements “n or more of (2n-1)” containing a group of first OR elements (1 ₁ , ... 1 _n ), a group of mod 2 addition elements (2 ₁ , ... 2 _n ), a group of first triggers (3 ₁ , … 3 _n ), group of first AND elements (5 ₁ , … 5 _n ), first OR element (8), counter (10), block (11) of majority elements “n or more of (2n-1)”, the inputs (24 ₁ , ... 24 _n ) of the device are connected to the first inputs of the first elements of the same name OR (1 ₁ , ... 1 _n ), characterized in that a group of second triggers (4 ₁ , ... 4 _n ), a group of delay elements ( 6 ₁ , … 6 _n ), a group of differentiating chains (7 ₁ , … 7 _n ), a trigger with a counting input (9), the outputs of the first OR elements (1 ₁ , … 1 _n ) are connected to the first inputs of the same addition elements mod 2 (2 ₁ , … 2 _n ), the outputs of which are connected to the first inputs of the first triggers of the same name (3 ₁ , … 3 _n ), the outputs of which are connected to the inputs of the same delay elements (6 ₁ , … 6 _n ) and differentiating chains (7 ₁ , … 7 _n ), the outputs of the differentiating chains (7 ₁ , … 7 _n ) are connected to the inputs of the same name of the first OR element (8), the output of which is connected to the input of the counter (10) and to the input of the trigger with a counting input (9), the output of which is connected to the first inputs of the first AND elements (5 ₁ , ... 5 _n ), the second inputs of which are connected to the outputs of the same delay elements (6 ₁ , ... 6 _n ), the outputs of the first AND elements (5 ₁ , ... 5 _n ) are connected to the inputs of the same second ones flip-flops (4 ₁ , … 4 _n ), the outputs of which are connected to the second inputs of the same name of the first flip-flops (3 ₁ , … 3 _n ) and to the second inputs of the first OR elements (1 ₁ , … 1 _n ), the output of device 22 is connected to the second inputs elements of addition mod 2 (2 ₁ , … 2 _n ).