RU2568304C2 - Method of clock synchronisation against data signals with crc test - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: method is related to the area of wireless engineering, and namely to radio communication equipment, and it may be used in data transmission systems using phase-shift keyed signals without redundancy in order to maintain synchronisation for phase-shift keyed signals or quadrature-amplitude modulated signals, in which code sequences block error-control codes and CRC are used. Essence of the method of clock synchronisation against data signals with CRC test lies in sequential demodulation of the received signal, decoding of code words with error correction and check-up of decoding fact by results of CRC calculation, i.e. remainder of division by polynom. With zero remainder CRC is calculated and added to the data block, coding is made with error-control code, modulation is made and cross-correlation function (CCF) is calculated for the signal received from the communication channel.

EFFECT: potential maintenance of clock synchronisation against data signal without transmission of auxiliary synchronising signals thus increasing transfer rate at the same running speed of transfer.

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Description

The invention relates to the field of electro-radio engineering, in particular to radio communication technology, and can be used in data transmission systems using phase-shifted signals, without introducing redundancy, to maintain (fine-tune) clock synchronization for signals with phase shift keying (PSK) or quadrature amplitude modulation ( KAM), in the code designs of which are used block error-correcting codes and CRC.

To ensure stable operation of data transmission systems, it is necessary to establish and maintain clock synchronization, i.e. determine the start and end time of the elementary signal.

There are many approaches to ensure the establishment and maintenance of clock synchronization. Most of them are based on the periodic transmission of test sync sequences that do not carry information, [SYNCHROINFO-2013 // Materials of the international scientific and technical seminar “Synchronization, signal generation and processing systems in infocommunications”, June 30 - July 3, 2013 / Ed. Doctor of Technical Sciences prof. A.V. Pestryakova. - M.: Bris-M LLC operational printing and design studio, 235 pp.]. This reduces the speed of information transfer, therefore, the use of information signals to maintain clock synchronization is promising.

Closest to the claimed technical solution is a method of joint clock and code synchronization (RF patent for the invention No. 2460219 of 02/10/2010), adopted as a prototype. The method of joint clock and code synchronization is that discrete information is received in the form of error correction code words within a sliding reception window sequentially shifted by one discrete sample, each time the sliding sliding window is shifted, error correction code words are decoded and the number of corrected errors with a predefined threshold value of the number of errors with the number of corrected errors less than the threshold, remember it and, in addition, remember the timestamp number and corresponding to the number of this discrete reference, and take discrete information with a shift of the sliding reception window in a time interval equal to the time interval of the code word. The fact of achieving clock and code synchronization is established at a time from the number of previously memorized time stamps corresponding to a discrete sample number with a minimum number of corrected errors from the number of discrete samples memorized in the entire time interval of the code word.

The disadvantages of the prototype include a greater number of computational operations due to the multiple decoding of the codeword with error correction for each successive shift of the sliding reception window by one discrete count, as well as the possibility of establishing false clock and loop synchronization in the case of decoding when shifting by one or more characters. In addition, the method calculates the number of errors after decoding, which involves the transmission of known information and, as a result, a decrease in the information rate.

The aim of the invention is to maintain clock synchronization during operation of a system for transmitting data by information signals, without interrupting the transmission of useful information.

This goal is achieved by the fact that in the method of clock synchronization for information signals with CRC verification, discrete information is received in the form of error correction code words, and CRC is computed and added to the information block transmitted from the message source, encoded by an error-correcting code, obtaining discrete information in the form code words, modulate and transmit the message signal over the communication channel, the signal received from the communication channel is demodulated, then the received discrete information in the form of code words, in which If there are errors, decode, calculate the CRC and, subject to error-free decoding, send the received information block to the message recipient, and also calculate and add the CRC, encode the error-correcting code, modulate it, and then the received signal is passed to the calculation unit of the autocorrelation function (ACF), then check the correlation properties of the received signal, and when ACF satisfying the given requirements, the signal is fed to the first input of the inter-correlation function calculation unit (VKF), to the second input of which the signal received from the communication channel, the calculation result of the VCF — an array of samples of the cross-correlation function — is transmitted to the decision block, in which the position of the maximum value in the array is determined, thus obtaining the desired position of the clock synchronization.

The structural diagram of the proposed device is shown in the drawing, where:

1 - message source;

2 - the first block add CRC;

3 - the first encoder;

4 - the first modulator;

5 - communication channel;

6 - demodulator;

7 - decoder;

8 - block check CRC;

9 - message recipient;

10 - second block add CRC;

11 - second encoder;

12 - second modulator;

13 - ACF calculation unit;

14 - condition check unit;

15 - unit calculation VKF;

16 - decision block.

The method of clock synchronization of information signals with CRC verification is as follows. An information block with a length of m bits is formed on the transmitting side in message source 1, for which CRC is calculated and added in the first block of adding CRC 2, after which the block length is k = m + s bits, where c is the number of CRC bits. The resulting block is encoded by an error-correcting code (n, k) in the first encoder 3, after which a code block of length n bits representing discrete information in the form of code words is modulated in the first modulator 4 and the received signal S (t) is transmitted to communication channel 5.

демодулируют в демодуляторе 6, получая принятую дискретную информацию в виде кодовых слов, в которой могут присутствовать ошибки, которую декодируют в декодере 7 и вычисляют CRC в блоке проверки CRC 8. Вычисление CRC есть деление на полином, остаток от деления показывает, присутствуют ли ошибки в декодированном блоке. Если остаток равен нулю, то считают, что декодирование в принимаемом кодовом блоке произошло без ошибок. В этом случае декодированный информационный блок длиной m бит передают получателю сообщений 9, а также вычисляют и добавляют CRC во втором блоке добавления CRC 10, кодируют во втором кодере 11 и модулируют во втором модуляторе 12. Сигнал с выхода второго модулятора 12 $$\overline{S}\left(t\right)$$

подают на вход блока вычисления АКФ 13. При этом при безошибочном декодировании сигнал $$\overline{S}\left(t\right)\equiv S\left(t\right)$$

. Автокорреляционную функцию на выходе блока вычисления АКФ 13 подают на вход блока проверки условия 14, где проверяют корреляционные свойства полученного сигнала $$\overline{S}\left(t\right)$$

и при удовлетворяющих заданным требованиям АКФ, таким как ширина главного лепестка и уровень боковых лепестков менее заданного порога, сигнал $$\overline{S}\left(t\right)$$

подают на первый вход блока вычисления ВКФ 15, на второй вход которого подают принимаемый из канала связи сигнал $$\tilde{S}\left(t\right)$$

. Результат вычисления ВКФ - массив отсчетов функции взаимной корреляции - передают в блок принятия решения 16, в котором определяют положение максимального значения в массиве, получая, таким образом, искомое положение тактовой синхронизации.At the receiving side, a signal received from communication channel 5 $$\tilde{S}\left(t\right)$$

demodulate in demodulator 6, receiving the received discrete information in the form of code words, which may contain errors, which are decoded in decoder 7 and calculate CRC in CRC 8. Calculation of CRC is a division by polynomial, the remainder of the division shows whether there are errors in decoded block. If the remainder is zero, then it is believed that the decoding in the received code block occurred without errors. In this case, the decoded information block with a length of m bits is transmitted to the message recipient 9, and the CRC is calculated and added in the second CRC adding block 10, encoded in the second encoder 11 and modulated in the second modulator 12. The signal from the output of the second modulator 12 $$\overline{S}\left(t\right)$$

fed to the input of the calculation unit ACF 13. In this case, with error-free decoding, the signal $$\overline{S}\left(t\right)\equiv S\left(t\right)$$

. The autocorrelation function at the output of the calculation unit ACF 13 is fed to the input of the verification unit of condition 14, where the correlation properties of the received signal are checked $$\overline{S}\left(t\right)$$

and when meeting the specified requirements of the ACF, such as the width of the main lobe and the level of the side lobes less than a predetermined threshold, the signal $$\overline{S}\left(t\right)$$

fed to the first input of the computing unit VKF 15, to the second input of which a signal received from the communication channel $$\tilde{S}\left(t\right)$$

. The result of computing the WKF — an array of samples of the cross-correlation function — is passed to decision block 16, in which the position of the maximum value in the array is determined, thus obtaining the desired position of the clock synchronization.

The proposed method allows to maintain clock synchronization directly on the information signals without transmitting additional synchronizing signals.

Claims (1)

The method of clock synchronization of information signals with CRC verification, which consists in receiving discrete information in the form of error correction codewords, characterized in that the CRC is computed and added to the information block transmitted from the message source, encoded with an error-correcting code, obtaining discrete information in the form of code words, they modulate and transmit the message signal over the communication channel, the signal received from the communication channel is demodulated, then the received discrete information in the form of code words, in which errors are present, decode, calculate the CRC and, subject to error-free decoding, the received information block is sent to the message recipient, and the CRC is calculated and added, encoded by an error-correcting code, modulated, after which the received signal is transmitted to the autocorrelation function (ACF) calculation unit, then the correlation properties are checked the received signal and, when ACF satisfying the given requirements, the signal is fed to the first input of the inter-correlation function calculation unit (VKF), to the second input of which inimaemy signal from the communication channel, the calculation result CCF - an array of samples crosscorrelation function - is transmitted to the decision block, wherein the determined position of the maximum value in the array to obtain thereby the desired position of the clock.