JP2015226197A - Frame synchronizing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frame synchronizing device capable of accurately detecting a starting position of a frame regarding a space-time coded signal.SOLUTION: An input signal includes a frame and a known sequence indicating the beginning of the frame and is coded with a space-time code defining N (N is a natural number equal to or greater than 2) symbols as one block. The frame synchronizing device includes: a delay section 3 for generating a delay input signal by giving delay of different delay times to the input signal for the unit of one symbol; decoding sections 6 and 7 each for outputting a decoded signal by decoding the input signal and the delay input signal with the space-time code; a detection section 8 for detecting the known sequence from any one of the decoded signals; and an extraction section 9 for selecting any one of the decoded signals on the basis of a detection result of the known sequence in the detection section and extracting the frame from the selected decoded signal.

Description

  The present invention relates to a frame synchronization technique in a communication apparatus.

Conventionally, in radio communication, many diversity methods using a plurality of transmission antennas and reception antennas for improving communication quality have been proposed. In transmission diversity, the transmitter transmits a signal using a plurality of antennas to obtain a diversity effect. There is a method using space time block codes (STBC) as one of transmission diversity. In STBC, for example, when two transmission antennas are used, a signal encoded in block units in which two symbols of a modulated signal are one block is transmitted from a transmitter. Then, STBC decoding of each block received by the processing using the channel estimation value is performed by the receiver, and a symbol before encoding is extracted.
Further, STBC has a problem that the processing load for obtaining a transmission path estimation value necessary for decoding processing is high, and a method using differential space-time code (DSTBC: Differential STBC) as a transmission diversity corresponding to this problem is proposed. (Non-Patent Document 1). In DSTBC, DSTBC encoding (DSTBC encoding) is performed using the block transmitted at the transmitter and the block transmitted immediately before (DSTBC encoding), and the DSTBC using the block received at the receiver and the block received immediately before is encoded. Decoding (DSTBC decoding) is performed to extract symbols before encoding.

V.Tarokh, H.Jafarkhani, "A Differential Detection Scheme for Transmit Diversity", IEEE Journal on Selected Areas in Communications, Vol.18, pp1169-1174, July 2000.

  In the receiver of the communication device, processing (frame synchronization) is performed to detect the start position of the frame (transmission frame) transmitted by the opposite transmitter. As a method of frame synchronization, a method of detecting a specific pattern (known sequence) known in a receiver such as a synchronization word (Sync Word) or a preamble is generally used. Hereinafter, such a known sequence used for frame synchronization is referred to as SW.

  In the above-mentioned DSTBC, encoding is performed by taking the difference between the block to be transmitted and the block transmitted immediately before, so that the signal point arrangement after encoding of the modulation signal of SW depends on the block transmitted immediately before Will change. For this reason, even if the SW has good detection accuracy before the DSTBC encoding, the detection accuracy may deteriorate after the encoding, and the start position of the frame is accurately identified for the DSTBC encoded received signal. There was a problem that was difficult.

  The present invention has been made to solve the above-described problem, and an object of the present invention is to provide a frame synchronization apparatus that can accurately detect the start position of a frame for a signal that is space-time encoded by DSTBC or the like. And

  The frame synchronization apparatus of the present invention includes a frame and a known sequence indicating the head of the frame, and for an input signal encoded with a space-time code having N symbols (N is a natural number of 2 or more) as one block, A delay unit that generates a delayed input signal with a delay having a different delay time in units of one symbol, a decoding unit that decodes the space-time code for the input signal and the delayed input signal, and outputs each decoded signal; A detection unit that detects a known sequence from any of the signals, and an extraction unit that selects any one of the decoded signals based on a detection result of the known sequence of the detection unit, and extracts the frame from the selected decoded signals; Are provided.

  According to the frame synchronization apparatus of the present invention, a space-time-encoded input signal having N (N is a natural number of 2 or more) symbols as one block and a delayed input signal obtained by delaying the input signal in units of one symbol, respectively. Since a known sequence indicating the beginning of a frame included in the input signal is detected from one of the decoded signals after decoding, the known sequence is detected from the signal decoded in units of space-time code blocks. Therefore, it is possible to perform frame synchronization with high accuracy for an input signal that is space-time encoded.

It is a block diagram which shows an example of a function structure of the frame synchronizer concerning Embodiment 1 of this invention. 4 is a flowchart illustrating an example of a processing flow of the frame synchronization apparatus according to the first embodiment. It is a schematic diagram which shows an example of the relationship between an input signal and the process timing of a decoding process part. It is a schematic diagram which shows an example of signal point arrangement | positioning before DSTBC encoding and after encoding. It is a block diagram which shows an example of a function structure of the frame synchronizer concerning Embodiment 2 of this invention. It is a block diagram which shows the modification of the function structure of the frame synchronizer of Embodiment 2 of this invention. It is a block diagram which shows an example of a function structure of the frame synchronizer concerning Embodiment 3 of this invention.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same or corresponding parts are denoted by the same reference numerals.
In the following description, DSTBC (Differential Space Time Block Codes) when two symbols are one block will be described as an example. However, the present invention does not limit the number of symbols in one block of DSTBC to two, and N ( N is a natural number greater than or equal to 2) The symbol may be one block.

Embodiment 1 FIG.
Embodiment 1 of the present invention will be described. FIG. 1 is a block diagram showing an example of a functional configuration of the frame synchronization apparatus 100 according to Embodiment 1 of the present invention. In FIG. 1, the frame synchronization apparatus 100 includes a delay unit 3, a decoding unit 4 and a decoding unit 5, a correlation processing unit 6 and a correlation processing unit 7, a detection unit 8, and an extraction unit 9. FIG. 1 also shows a configuration of a receiving apparatus to which the frame synchronization apparatus 100 is applied. The receiving apparatus includes a frame synchronization apparatus 100, a reception antenna 1, a reception processing unit 2, and a determination unit 10.

  Each of the above-described blocks included in the frame synchronization apparatus 100 can be realized by hardware using an ASIC (Application Specific Integrated Circuit), or a peripheral circuit such as a memory is connected to at least a part of the above-described blocks. It is possible to implement with a processor and a program executed on the processor.

  The reception antenna 1 receives a DSTBC-encoded radio signal transmitted from the opposite transmitter, and the reception processing unit 2 performs reception processing such as frequency conversion and band limitation on the radio signal received by the reception antenna 1. Implement an output signal that is a signal whose transmission rate is a symbol rate. The input signal is input to the delay unit 3 and the decoding unit 4 of the frame synchronization apparatus 100. The delay unit 3 outputs a delayed input signal obtained by adding a delay (one symbol time) required for transmission of one symbol to the input signal output from the reception processing unit 2. Here, the input signal is a symbol rate, but it is not necessarily a symbol rate, and a delayed input signal to which a time delay required for transmission of one symbol at the input signal transmission speed is added is output. It only has to be.

  The decoding unit 4 performs DSTBC decoding on the input signal in units of signals for two symbols, and outputs a decoded signal (first decoded signal). The decoded signal is input to the correlation processing unit 6, and the correlation processing unit 6 outputs a correlation value (first correlation value) obtained from the correlation between the decoded signal and SW. Similarly, the decoding unit 5 performs DSTBC decoding on the delayed input signal and outputs a delayed decoded signal (second decoded signal), and the correlation processing unit 7 obtains the correlation between the delayed decoded signal and SW. A correlation value (second correlation value) is output. Hereinafter, a system for processing an input signal is referred to as a first processing system, and a system for processing a delayed input signal is referred to as a second processing system.

  The detection unit 8 detects the SW of the decoded signal or the delayed decoded signal based on the correlation value, the delay system correlation value, and the set threshold value, and the processing system that detects the SW (that is, the decoded signal and the delayed decoded signal). SW detection information indicating any one of them and the SW detection position is output. The extraction unit 9 extracts and outputs a frame (reception frame) received from the decoded signal or the delayed decoded signal according to the SW detection information.

  The reception frame output from the extraction unit 9 is input to the determination unit 10, and the determination unit 10 performs demodulation processing (first determination processing) for determining a signal transmitted from the transmitter facing the reception frame, and demodulates the received frame. Output data.

  Next, the operation of the frame synchronization apparatus 100 will be described. First, a signal (input signal) input to the frame synchronization apparatus 100 will be described. As for the input signal, the reception processing unit 2 performs reception processing such as analog-digital conversion (A / D conversion), frequency conversion, band limitation, symbol timing reproduction, and the like on the analog radio signal received by the receiving antenna 1. It is a digital signal of the symbol rate obtained in The reception processing performed by these reception processing units 2 may be performed by a known processing method.

  An input signal obtained by the reception processing unit 2 is input to the delay unit 3 and the decoding unit 4 of the frame synchronization apparatus 100. FIG. 2 is a flowchart showing a processing flow of the frame synchronization apparatus 100 of this embodiment that has received an input signal. This flowchart is shown as an example, and for example, it may be pipelined so that each step is executed in parallel.

  The delay unit 3 delays the received input signal by one symbol time, and outputs a delayed input signal (ST1). Since the input signal is a signal that is DSTBC encoded with two symbols as one block, when the input signal has a symbol rate, for example, one block is shown as block A, block B, and block C in FIG. It is transmitted using 2 symbol times. On the other hand, the decoding unit 4 and the decoding unit 5 perform the DSTBC decoding process at a cycle of 2 symbol times, such as cycles X, X + 1, and X + 2 shown in FIG. At this time, for example, there is a possibility that the timing is shifted by one symbol time as in the block A shown in FIG. 3A and the period X shown in FIG.

  According to the frame synchronization apparatus 100 of this embodiment, by generating a delayed input signal obtained by delaying the input signal by one symbol time as described above, one of the input signal and the delayed input signal is a decoding unit. 4 or the execution timing of the DSTBC decoding process in the decoding unit 5 and the boundary of the block coincide with each other, and the DSTBC decoding process for each block can be performed in the matching processing system. A state in which the timing of the DSTBC decoding process matches the block boundary in this way is hereinafter referred to as block synchronization.

  The decoding unit 4 extracts data for 2 symbols from the input signal, performs DSTBC decoding using the data for 4 symbols together with the data for 2 symbols extracted in the previous decoding process, and obtains a decoded signal (ST2 ). Similarly, in ST2, the decoding unit 5 similarly extracts 2-symbol data from the delayed input signal, performs DSTBC decoding using the 4-symbol data together with the 2-symbol data extracted in the previous process, and performs delay. A decoded signal is obtained. Here, the DSTBC decoding process performed by the decoding unit 4 and the decoding unit 5 may be performed by the method described in Non-Patent Document 1, for example.

  This embodiment is an example in which one block is 2 symbols. However, when 1 block of DSTBC is N symbols, the input signal is in units of 1 symbol from 1 symbol time to N-1 symbol time. N-1 delayed input signals with different delay times may be generated, and N processing systems may be provided together with the input signals.

  Correlation processing unit 6 obtains the correlation with SW for the DSTBC decoded decoded signal on the complex plane and outputs the correlation value (ST3). Here, it is assumed that the correlation value is a ratio that matches the SW. In ST3, correlation processing unit 7 similarly obtains and outputs a correlation value (delay system correlation value) with SW for the delayed decoded signal. Since either the first processing system or the second processing system is a block-synchronized signal, and the block-synchronized processing system can perform DSTBC decoding for each block, the correlation value and the delay system correlation value Either one can obtain a high correlation.

  Since the decoded signal is a signal modulated by BPSK (two-phase shift keying) or QPSK (four-phase shift keying), it is necessary to obtain a correlation value with SW also being modulated. With respect to the SW in the modulated state, the correlation processing unit 6 may perform modulation processing on the SW sequence, may store the SW that has been in the modulated signal state in advance, or otherwise may include the SW sequence. It is also possible to make a configuration such that the signal is modulated and input to the correlation processing unit 6. The same applies to the delayed decoded signal.

  The detection unit 8 detects SW based on the correlation value obtained by the correlation processing unit 6 and the correlation processing unit 7 and the delay system correlation value, and outputs the detection result as SW detection information (ST4). Specifically, when the correlation value and the delayed correlation value are equal to or greater than a set threshold value, the processing system that is equal to or greater than the threshold value and the SW position information in the decoded signal of the processing system ( SW detection position) is output as SW detection information. If the correlation value exceeds the threshold value in two processing systems at the same time, either one of the processing systems is given priority, the one with the higher correlation value is selected, or in a certain period. One processing system may be selected by, for example, selecting a processing system in which the number of times that the correlation value is equal to or greater than the threshold value is greater than a certain number. If a processing system is selected in which the number of times that the correlation value is equal to or greater than the threshold value in a certain period is selected, an effect of reducing the false detection probability of SW can be expected.

The extraction unit 9 selects either the decoded signal or the delayed decoded signal according to the SW detection information output from the detection unit 8, and extracts and outputs a received frame from the selected signal with reference to the SW detection position (ST5). . The reception frame output from the extraction unit 9 may or may not include SW.
The detection unit 8 and the extraction unit 9 only need to have a function of detecting the SW and extracting and outputting the received frame from the decoded signal or the delayed decoded signal. The SW detection information output by the detection unit 8 The timing reflected in the process may be any timing. Furthermore, the start position of the reception frame output from the extraction unit 9 to the determination unit 10 may be started from an arbitrary position, for example, immediately after the SW detection position.

  And the determination part 10 performs a determination process about the received frame which the extraction part 9 output. Here, the determination process is a process for determining what the data transmitted by the opposite transmitter is, and may be a hard determination or a soft determination. The determination unit 10 outputs the result of the determination process as demodulated data. Even if the determination unit 10 is arranged upstream of the extraction unit 9, the same effect as in this embodiment can be obtained.

  As described above, the frame synchronizer of this embodiment performs DSTBC decoding on both the DSTBC-encoded input signal and the delayed input signal obtained by delaying the input signal by one symbol time, Correlation with SW is obtained, SW is detected from the decoded signal of the input signal or delayed input signal based on the obtained correlation, frame synchronization is performed, and received frames are extracted from the frame-synchronized signal. .

As a result, for either the input signal or the delayed input signal, it is possible to perform the decoding process in a block synchronization state in which the processing timing of the decoding process and the boundary of the DSTBC block coincide with each other, and the input signal encoded with DSTBC can be accurately Frame synchronization can be performed.
Also, as shown in FIG. 4, after DSTBC encoding, the distance between signal points is shorter than before encoding, but since SW is detected in a state returned before DSTBC encoding, Frame synchronization can be performed by accurately detecting SW in a long distance state.
Also, frame synchronization can be achieved by a simple process in which the input signal and the delayed input signal are each DSTBC decoded, the correlation between the decoded signal and the SW is obtained, and the SW is detected based on this correlation.

  In this embodiment, the input signal is delayed by one symbol time to generate a delayed input signal and the decoding unit 5 performs the decoding process. However, the same signal as the decoding unit 4 is input to the decoding unit 5, It is also possible to change the configuration so that the processing timings of the decoding unit 4 and the decoding unit 5 are shifted by one symbol time.

  In this embodiment, the correlation processing unit 6 and the correlation processing unit 7 perform processing for the first processing system and the second processing system, respectively, but the sum of the signal power of the symbols in the block is constant. The sum of signal power for each of the two processing systems is calculated for each of the two processing systems using the property of DSTBC encoding, and the processing system with the smaller dispersion value of the calculation result is selected as the block-synchronized processing system. It is also possible to adopt a configuration in which a received signal with frame synchronization is obtained by correlating the processing system.

  In the above-described embodiment, the input signal encoded by DSTBC has been described. However, DSTBC may be replaced with STBC.

Embodiment 2. FIG.
Next, a second embodiment of the present invention will be described. FIG. 5 is a block diagram showing an example of a functional configuration of the frame synchronization apparatus 100a according to Embodiment 2 of the present invention. The difference between the frame synchronization apparatus 100 shown in FIG. 1 and the frame synchronization apparatus 100a of FIG. 5 in the description of the first embodiment is between the decoding unit 4 and the correlation processing unit 6, and between the decoding unit 5 and the correlation processing unit 7. It is a point provided with the determination part 11 and the determination part 12 which perform a temporary determination process (2nd determination process) to the signal each decoded between. In this embodiment, the correlation processing unit 6 and the correlation processing unit 7 perform the processing for obtaining the correlation as in the first embodiment, but the processing target is the signal processed by the determination unit 11 and the determination unit 12. .

  Next, the operation of the frame synchronization apparatus 100a of this embodiment will be described. Note that the processing from reception of an analog radio signal by the receiving antenna 1 to the processing of the decoding unit 4 and the decoding unit 5 is the same as that of the first embodiment, and the processing after the detection unit 8 and the extraction unit 9 is also the first embodiment. Therefore, the description will be made by paying attention to the difference from the first embodiment.

  The determination unit 11 and the determination unit 12 perform provisional determination on the decoded signals output from the decoding unit 4 and the decoding unit 5, respectively. The provisional determination process may be either hard determination or soft determination. Alternatively, one axis passing through the origin may be created on the complex plane, and whether the decoded signal is positive or negative with respect to that axis may be determined. When performing positive / negative determination, for example, positive / negative is determined for the in-phase component of the modulation signal, such as BPSK, and 0 is output if negative and 1 is output if positive.

  The correlation processing unit 6 and the correlation processing unit 7 calculate the correlation with the SW series for the signals that have been provisionally determined by the determination unit 11 and the determination unit 12, respectively. When the determination unit 11 and the determination unit 12 make a hard decision or a soft decision, the SW may be used as it is in the sequence to obtain the correlation. When the positive / negative determination is made, the SW sequence is modulated as in the first embodiment, and then the correlation with the result of the positive / negative determination of the modulated signal is obtained. At this time, as for the positive / negative determination result of the signal obtained by modulating the SW series, the calculation amount can be reduced by storing the determination result obtained in advance in a memory.

  In the positive / negative determination, particularly when modulation with a large number of values per symbol such as 8PSK or 16QAM is used, the processing amount of the determination can be reduced as compared with the hard determination or the soft determination. For example, when the modulation signal is 16PSK, the signal point is represented by A × exp (2πi × (22.5 × n + 11.25) ÷ 360), A is the amplitude of the modulation signal, and n is 15 or less including 0 When i is an imaginary number unit and i is an imaginary unit, the SW sequence is composed only of signal points of n = 0, 7, 8, 15 having the largest absolute value of the in-phase component. By selecting so that the accuracy of SW detection can be improved.

  The detection unit 8 outputs SW detection information on the assumption that the SW is detected when the first or second correlation value obtained in the same manner as in the first embodiment is a certain value or more. In addition, when the determination unit 11 and the determination unit 12 use the hard determination or the positive / negative determination, the SW can be detected when the number of bits that do not match the total number of SW bits is equal to or less than a certain value. good. Extraction unit 9 and determination unit 10 perform the same processing as in the first embodiment and output demodulated data.

As described above, the frame synchronization apparatus according to this embodiment performs DSTBC decoding on both the DSTBC-encoded input signal and the delayed input signal obtained by delaying the input signal by one symbol time, and each of the decoded signals. After the determination, the correlation with SW is obtained, SW is detected from the decoded signal of the input signal or delayed input signal based on the obtained correlation, frame synchronization is performed, and the received frame is extracted from the frame-synchronized signal I tried to do it.
As a result, in addition to the effects described in the first embodiment, the correlation processing unit only has to obtain the correlation for the demodulated signal instead of the modulated signal, so that the processing amount of the correlation processing unit can be reduced. The effect of becoming.

As a modification of this embodiment, the signals subjected to the determination processing by the determination unit 11 and the determination unit 12 as in the frame synchronization apparatus 100b shown in FIG. 6 are input to the correlation processing unit 6 and the correlation processing unit 7, respectively. You may make it input into the extraction part 9. FIG.
In such a case, the determination unit 11 and the determination unit 12 perform hard determination or soft determination. Further, the extraction unit 9 extracts the received frame from the demodulated signal after the determination processing output from the determination unit 11 and the determination unit 12 according to the SW detection information output from the detection unit 8 and outputs the received frame as demodulated data. In this case, the determination unit 10 shown in FIG. 5 is not necessary.

Embodiment 3 FIG.
Next, a third embodiment of the present invention will be described. FIG. 7 is a block diagram showing an example of a functional configuration of the frame synchronization apparatus 100d according to this embodiment. 7, the same reference numerals as those in FIG. 1 are the same as those in the first embodiment. The frame synchronization apparatus 100d of this embodiment is different from that of Embodiment 1 in that it includes a delay unit 21, a decoding unit 22, and a decoding unit 23. In this embodiment, in addition to the input signal shown in Embodiment 1, in addition to the input signal shown in Embodiment 1, the reception antenna 19 and the reception processing unit 20 receive the reception antenna for the signal transmitted from the opposite transmitter by DSTBC encoding and wirelessly transmitted. 1 and the second input signal that has been processed in the same manner as the reception processing unit 2 is input.

  The delay unit 21 delays the input second input signal by one symbol time in the same manner as the delay unit 3 and outputs a second delayed input signal. The decoding unit 22 receives the input signal and the second input signal, performs reception diversity processing on the two input signals, and performs DSTBC decoding similar to that in the first embodiment. In addition, the decoding unit 23 receives the delayed input signal and the second delayed input signal, performs DSTBC decoding after performing reception diversity processing in the same manner as the decoding unit 22. The subsequent correlation processing unit 6, correlation processing unit 7, detection unit 8 and extraction unit 9 are the same as those in the first embodiment. The determination unit 10 is the same as that in the first embodiment.

  Next, the operation of the frame synchronization apparatus 100d of this embodiment will be described focusing on the differences from the first embodiment. The processing of the receiving antenna 1 is the same as that of the first embodiment, and the receiving antenna 19 performs the same processing as that of the receiving antenna 1. The processing of the reception processing unit 2 is the same as that of Embodiment 1, and outputs an input signal to the frame synchronization apparatus 100d. The reception processing unit 20 performs the same processing as the reception processing unit 2 and outputs the second input signal to the frame synchronization apparatus 100d. The processing of the delay processing unit 3 is the same as that of the first embodiment, and outputs a delayed input signal. The processing of the delay unit 21 is the same as that of the delay unit 3, and outputs a second delayed input signal obtained by delaying the second input signal.

  The decoding unit 22 receives the input signal and the second input signal, and the decoding unit 22 performs DSTBC decoding similar to that of the decoding unit 4 of the first embodiment after receiving diversity processing of the two input signals. . Similarly, the decoding unit 23 receives the delayed input signal and the second delayed input signal, and performs the DSTBC decoding similar to the decoding unit 5 of the first embodiment after receiving diversity processing of the two input signals. In the reception diversity processing, either of the input signals may be selected, or the input signals may be combined.

In this example, the case where the input signal based on the signal received by the receiving antenna 1 and the second input signal based on the signal received by the receiving antenna 19 are input has been described. However, the signal is received by three or more antennas. Even when three or more input signals based on the received signals are input, the same configuration can be used.
The processes of the correlation processing unit 6, the correlation processing unit 7, the detection unit 8, and the extraction unit 9 are the same as those in the first embodiment. Further, the processing of the determination unit 10 is the same as that of the first embodiment.

As described above, in the frame synchronization apparatus of this embodiment, a plurality of input signals based on signals received by a plurality of receiving antennas are input, and a delay input that is delayed by one symbol time from each of the plurality of input signals. Signals are generated, input signals are subjected to reception diversity processing, delay input signals are subjected to reception diversity processing, DSTBC decoding of the signals after each reception diversity processing is performed, and a correlation between each of the signals after DSTBC decoding and SW is correlated. Then, SW is detected from the decoded signal or the delayed decoded signal based on the obtained correlation, frame synchronization is performed, and a received frame is extracted from the frame-synchronized signal.
Thereby, in addition to the effect shown in Embodiment 1, it becomes possible to perform frame synchronization by a simple process even when the number of receiving antennas is two or more.

  Note that the same configuration as that of the third embodiment can be applied to the synchronization device 100b and the synchronization device 100c described in the second embodiment.

  In this embodiment, the reception diversity processing is performed in the decoding unit 22 and the decoding unit 23. However, after the reception diversity processing is performed on the first input signal and the second input signal, the input shown in the first embodiment is performed. It can also be configured to be a signal.

  1,19 reception antenna, 2,20 reception processing unit, 3,21 delay unit, 4, 5, 22, 23 decoding unit, 6,7 correlation processing unit, 8 detection unit, 9 extraction unit, 10, 11, 12 judgment Part, 100, 100a, 100b, 100c, 100d Frame synchronization apparatus.

Claims (7)

A delay time in units of one symbol with respect to an input signal including a frame and a known sequence indicating the head of the frame and encoded with a space-time code having N symbols (N is a natural number of 2 or more) as one block A delay unit that generates a delayed input signal with different delays, and
A decoding unit that decodes the space-time code for the input signal and the delayed input signal and outputs the decoded signals;
A detection unit for detecting the known sequence from any of the decoded signals;
An extraction unit that selects any one of the decoded signals based on the detection result of the known sequence of the detection unit and extracts the frame from the selected decoded signal;
A frame synchronization device comprising:   The frame synchronization apparatus according to claim 1, wherein the space-time code is a differential space-time code. The delay unit generates N-1 delayed input signals obtained by adding delays having different delay times up to N-1 symbols in units of one symbol.
The decoding unit performs the decoding of the input signal and the N-1 delayed input signals and outputs N decoded signals.
The frame synchronization apparatus according to claim 1 or 2, wherein A determination unit that performs a determination process of the decoded signal;
The detection unit detects the known sequence based on a determination processing result of the determination unit;
The frame synchronization apparatus according to any one of claims 1 to 3, wherein the frame synchronization apparatus is characterized.   5. The determination unit according to claim 4, wherein the determination unit determines the decoded signal based on whether the decoded signal is in a positive or negative direction with respect to an axis centered on an origin on a complex plane. The frame synchronizer described.   5. The frame synchronization apparatus according to claim 4, wherein the extraction unit extracts the frame from a signal obtained by performing determination processing on the decoded signal output from the determination unit. The delay unit generates the delayed input signal from each of the plurality of input signals received by different antennas,
The decoding unit performs reception diversity processing on the plurality of input signals, performs reception diversity processing on the signals having the same delay time provided among the delayed input signals generated from the plurality of input signals, respectively, Performing the decoding on the signal after the reception diversity processing and outputting the decoded signal,
The frame synchronization apparatus according to any one of claims 1 to 6, wherein the frame synchronization apparatus is characterized in that

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