RU2549231C1 - Method of linearised signal shaping on missile rotating by bank angle signal lineariser switchable signal lineariser integration method for linearised signal shaping and digital integrator for its implementation - Google Patents

Abstract

FIELD: aviation.

SUBSTANCE: in the method of linearised signal shaping, the rotation period of missile is divided into time intervals on the missile rotating by bank angle, their durations are measured and stored in a certain way. Signal lineariser comprises digital integrator, calculator, tilt signal shaper, step-signal shaper, register and clock-pulse driver. Switchable signal lineariser comprises digital integrator, two calculators, tilt signal shaper, step-signal shaper, tilt sensor, register, control unit, switchboard, clock-pulse driver. In the process of integration, the amplitude of clock pulses is integrated on the missile rotating by bank angle in order to shape the linearised signal, bit-by-bit summing of bitwise binary parallel numbers for each rising edge of clock pulses is carried out. Duration of integration interval is set of corresponding duration of angular spacing of 90 degrees. Then, the integration process is repeated, by changing the discrete quantity in a certain way before starting. Digital integrator comprises series-connected single-bit digital cells. Cell contains D-flip-flop and adder connected in a certain way.

EFFECT: high precision of control command shaping by missile.

11 cl, 7 dwg

Description

The invention relates to a method and control systems for aircraft rotating in a roll angle, and can be used in missile control systems forming control commands on board, for example, television guidance in the beam.

There is a method of generating a linearized signal on a rocket rotating in a roll angle and a signal linearizer based on it [Russian patent No. 2282129 of 08.20.06, MKI ⁷ F41G 7/00], selected as prototypes. A known method of generating a linearized signal on a rocket rotating in a roll angle, comprising generating a roll angle of pulses mounted on a rocket, in which the period of rotation of the rocket in roll angle is divided into time intervals corresponding to one quarter of the roll period, the duration of the current time interval is measured and stored.

The known linearizer of the signal comprises a roll sensor, a calculator, an integrator, and a roll shaper and a step shaper, the first and second outputs of the roll sensor are connected respectively to the first and second inputs of the roll shaper.

As follows from the above, the magnitude of the magnitude, i.e. the amplitude from peak to peak, the linearized signal at the output of the linearizer for each quarter of the roll period is

where τ is the integration time constant,

T is the duration of the time interval.

Since the discrete amplitude value A = A _i-1 = A _i = const in each quarter of the bank period, when summing the value of the quantity A from expression (1) with the value minus A / 2 for a quantity, for example, A = 2B and t _i = T _i-1 , the value of the magnitude of the amplitude of the linearized signal will vary from minus 1B to + 1B. Thus, at a constant value of the angular velocity of the rocket’s rotation along the roll angle, the linearized signal is symmetrical with respect to zero, and its magnitude is equal to the specified value, i.e. 2B. However, when accelerating or slowing the rotation of the rocket along the roll angle, for example, reducing t _i relative to T _i-1 by 10% according to expression (1), taking into account the summation, the linearized signal will change from minus 1B to + 0.8B, i.e. asymmetrically with respect to zero, and its magnitude of 1.8B will not be equal to the specified value, i.e. 2B.

The rocket from the moment of launch to the moment it hits, for example, a beam (in the television guidance system) is controlled autonomously. In this case, the pulse-width modulated (PWM) control command generated on the rocket, for example, in pitch, equal to zero during accelerated or slowed motion of the rocket, is distorted. In this case, instead of a zero command, 0.1 units are formed. commands according to the example above.

Thus, in the known technical solution, which generates a linearized signal according to the length of the previous roll impulse, an error occurs when the roll impulse duration changes, the magnitude of which is greater, the greater or less (negative sign) the rocket accelerates along its flight path.

Therefore, the disadvantage of the known method of generating a linearized signal on a rocket rotating in an angle of roll and the known linearizer of a signal based on it is the insufficiently high accuracy of forming a linearized signal when the flight speed (acceleration) of the rocket changes.

A known method of integration for the formation of a linearized signal [L. Falkenberry "The use of operational amplifiers and linear ICs", M .: Mir, pp. 126-132, Fig. 6.2, 6.4, prototype], in which the amplitude of the linearized signal is integrated in a time interval equal to the duration of the angular interval. The known method involves setting the zero logic level in the initial state of the integrator at the outputs of D-flip-flops and inputting an input k-bit binary parallel number to the inputs of the adders.

Known shift register with parallel input [U. Titze, K. Schenk “Semiconductor circuitry”, Moscow, Mir, 1983, p. 356 Fig. 20.18 prototype], where a method and device for increasing (integrating, for example, in time) a binary number in parallel form are used. A device that implements the known integration method contains "n" series-connected single-digit cells, each of which includes a D-trigger, adder.

In a known technical solution, the maximum value of a binary number is determined by the number of "n" cells. In this case, the value of the output binary number in the initial state is set equal to zero (0000). And then the first clock pulse (its edge) writes to the D-flip-flops a binary parallel number, for example 0001, by entering it. Subsequent clock pulses increase it (when shifted to the right), respectively, in two (2 ¹ ), four (2 ² ), eight (2 ³ ), etc. times (with the appropriate number of cells). Thus, the change in the output signal is non-linear, except for the first three values: 0, 2 ⁰ and 2 ¹ , which impairs the accuracy of the formation of the linearized signal of the angle of heel.

Therefore, the disadvantage of the known method of integrating a binary number in parallel and the device that implements it is a small linear zone of the output signal, which must be adjusted, for example, using a programmable memory device. This imposes a restriction on the application of the known technical solution.

The objective of the proposed group of inventions is to increase the accuracy of the formation of a linearized signal on a rocket rotating in an angle of roll, by eliminating or reducing the amplitude of the linearized signal when accelerating or slowing the flight of the rocket, as well as increasing the linearity of the linearized signal, which generally improves the accuracy of formation of rocket control commands.

как $$\frac{1}{T_i}=\frac{2}{T_{i-1}}-\frac{1}{T_{i-2}}$$

, где T_i - последующая длительность временного интервала, i=0, 1, 2, и т.д., при этом величину $$\frac{1}{T_i}$$

умножают на A=const - заданная дискретная величина амплитуды линеаризированного сигнала, и в течение изменения временного интервала от 0 до t_i, соответствующего величине углового интервала равного четверти кренового периода вращения ракеты, величину $$A•\frac{1}{T_i}$$

интегрируют, после чего процесс повторяют вновь.The problem is achieved in that in the method of generating a linearized signal on a rocket rotating along the roll angle, which includes forming a roll angle of pulses mounted on the rocket, in which the period of rotation of the rocket along the roll angle is divided into time intervals corresponding to one quarter of the roll period, measurement and storage duration of the current time slot T _i-1, new is the fact that, before the memorization of the duration of this time interval is stored its previous The shutter duration T _i-2, and calculating the magnitude $$\frac{\mathrm{one}}{T_i}$$

as $$\frac{\mathrm{one}}{T_i}=\frac{2}{T_{i-\mathrm{one}}}-\frac{\mathrm{one}}{T_{i-2}}$$

, where T _i - the subsequent duration of the time interval, i = 0, 1, 2, etc., while the value $$\frac{\mathrm{one}}{T_i}$$

multiplied by A = const - the given discrete value of the amplitude of the linearized signal, and during the change in the time interval from 0 to t _i corresponding to the value of the angular interval equal to a quarter of the roll period of rocket rotation, the value $$A•\frac{\mathrm{one}}{T_i}$$

integrate, after which the process is repeated again.

A signal linearizer comprising an integrator, a calculator, a roll signal shaper and a step shaper, a roll sensor, the first and second outputs of which are connected to the corresponding inputs of a roll shaper, the new one is that a register and a clock shaper are introduced into it, and the integrator is made digital, while the input of the pulse shaper is connected to the third output of the shaper of the stepped signal, and the output is connected to the clock input of the integrator, the register write progress is connected to the fourth output of the step signal former, the information output of the register is connected to the second information input of the calculator, and the register information together with the first information input of the calculator is connected to the second output of the step signal shaper, the information output of the calculator is connected to the information input of the integrator, input zeroing which is connected to the first which is the control output of the shaper of the stepped signal. The pulse generator is designed as a digital frequency divider. The step signal shaper is made in the form of a synchronizer, a shaper register, an “I” logic circuit, a pulse counter, sequentially connected first, second and third pulse shapers, an “RS” trigger, while the invertible output of the “RS” trigger and the shaper register output are respectively, the first and second outputs of the stepper signal shaper, the synchronizer output and the first input of the logic circuit "And" are the third output of the stepped signal shaper, the fourth output of which is the first input of the "RS" -trigger and the first output of the first pulse shaper.

A switchable signal linearizer comprising an integrator, a calculator, a roll signal shaper and a step shaper, a roll sensor, the first and second outputs of which are connected to the corresponding inputs of the roll shaper, the new one is that a register, a control unit, a switch are introduced into it , the second calculator and generator of clock pulses, and the integrator is made digital, while the input of the generator of clock pulses is connected to the third output of the generator step signal, and the output is with the integrator clock input, made as digital, while the first information input of the second calculator and the information input of the register together with the information input of the first calculator are connected to the second output of the step signal shaper, the information output of the register is connected to the second information input of the second calculator the information output of which is connected to the second information input of the switch, the first information input of which is connected to the information output m of the first calculator, the information output of the switch is connected to the information input of the integrator, and the control input of the switch is connected to the output of the control unit, the input of which is connected to the first output of the roll sensor, the input of the register entry is connected to the fourth output of the step signal shaper, the first output of which is connected to the zeroing input integrator. The pulse generator is designed as a digital frequency divider. The step signal shaper is made in the form of a synchronizer, a shaper register, an “I” logic circuit, a pulse counter, sequentially connected first, second and third pulse shapers, an “RS” trigger, while the invertible output of the “RS” trigger and the shaper register output are respectively, the first and second outputs of the stepper signal shaper, the synchronizer output and the first input of the logic circuit "And" are the third output of the stepped signal shaper, the fourth output of which is the first input of the "RS" -trigger and the first output of the first pulse shaper. The control unit is designed as an “RS” trigger, the R-input of which is connected to the first output of the roll sensor, and the S-input is with the output of the onboard power supply. The switch is made as two identical electronic keys.

The technical result is also achieved by the fact that, an integration method for generating a linearized signal on a rocket rotating in a roll angle, including integration in a time interval equal to the duration of the angular interval, the amplitude of the clock pulses, setting the logic level to zero at the outputs of the D-flip-flops and inputting a parallel-bit binary number at the inputs of adders, new is the fact that the first inputs of the adders fed a _i corresponding to the value of each bit of the input to the time- yadnogo binary parallel numbers are bitwise summed in each subsequent respective adder on a second of its inputs b _{i + 1} with the values of bits of the binary parallel numbers C _i transfer outputs _{+ 1} of each of the previous adder, stored value of the total of the parallel binary number at the output the sum S _i corresponding to each adder at the moment of formation of the first front of the rise of clock pulses, and then additionally sum the stored values of each bit of the binary parallel number, after upayuschego to transfer inputs c _i data adders, with the values of the sums of the first input a _i with the second b _i, where i = 1, 2, ... k - number of bits of the binary parallel number (from least to most), then the summation cycle is repeated many times at the moments of the formation of the second and subsequent fronts of rise of clock pulses, and the duration of the integration interval is set corresponding to the duration of the angular interval equal to 90 °, at the end of which the logic level is set at the outputs of the D-flip-flops, and then the integration process is repeated again, and with each summation cycle, the current value of the output binary binary number, the discharges of which are formed at the outputs of the D-flip-flops, is increased by a constant discrete value of the amplitude, the number of discrete values of which is limited to a predetermined value corresponding to the duration of the angular interval, the discrete value is changed before starting the integration process, in which the input k-bit binary parallel number is updated.

A digital integrator containing "n" series-connected digital one-bit cells, each of which includes a D-trigger, an adder, the new one is that the adder is a two-input, the sum output of which is connected to the information input of the D-trigger, the information output of which is from the cell is connected to the information input from the previous cell, the output of the D-trigger is connected to the adder transfer input, which from each previous digital one-bit cell is connected to the second adder input from each subsequent a single-bit cell, the first adder inputs from all digital single-bit cells being connected together and being the information input of the digital integrator, the second adder input from the first digital one-bit cell and the first adder input from the last one-bit cell are not borrowed and connected to the case, and the outputs of D triggers from the corresponding cells are combined and are the output of a digital integrator.

The claimed method of forming a linearized signal on a rocket rotating in a roll angle is implemented as follows. From the moment of launch, the rocket begins to rotate along the angle of heel, for example, due to the rotation of the stabilizer blades. In this case, the roll angle sensor mounted on the rocket generates impulses. These pulses are two logical signals, unit and zero, whose logical levels are equal to angular intervals of 180 °, and the repetition period of each of them corresponds to 360 °. Moreover, these two logical signals are phase shifted relative to each other by 90 °. Using these two logical signals, the roll period (angular interval 0 ° ... 360 °) is divided into time intervals corresponding to one quarter of the roll period i.e. 0 ° ... 90 °, 90 ° ... 180 °, 180 ° ... 270 °, 270 ° ... 360 °.

A missile flight is a helical movement composed of rectilinear translational motion with a velocity υ and rotation around its axis with an angular velocity of rotation ω, for example, due to stabilizers creating rotational motion. ["Physical Encyclopedic Dictionary". Ch. Editor A.M. Prokhorov, Moscow, "Sov. Encyclopedia" 1984, p.77], while

where p is the screw parameter.

With uniformly accelerated or uniformly slowed-down rocket movement in the section of velocity change from υ ₀ to υ _{t, the} average (intermediate) speed υ _cp will be defined as

Where from

Therefore, by measuring the quantities υ ₀ and υ _cf, it is possible to determine the expected value of the speed υ _t .

Thus, with uniformly accelerated or uniformly slowed-down rocket flight, i.e. with a linear or close to linear change in flight speed, knowing two values of the angular velocity (rocket rotation speed according to the angle of heel): ω _i-2 - previous (corresponding to the initial speed υ ₀ ) and ω _i-1 - current (corresponding to the average speed υ _{cp .} ), taking into account expression (4), it is possible to uniquely calculate the value of the subsequent (future) angular velocity ω _i - the next (corresponding to the final υ _t ) without taking into account the constant value of the coefficient p (screw parameter).

where i = 0 ... n every previous (i-2), current (i-1) and subsequent (future - i) quarters of the rocket’s rotation periods along the roll angle, each of which corresponds to an angular interval of 90 °, and determines the values of the corresponding angular velocities .

Given that

Substituting them into expression (4) we obtain for each quarter of the heeling period

, используя выражение (7), где T_i - последующая (будущая) длительность временного интервала, i=0, 1, 2 и т.д., при этом при вычислении дополнительно умножают величину $$\frac{1}{T_i}$$

на A_i=A=const согласно выражению (1).Thus, the duration of the current time interval T _{i-1 is} measured and stored. Moreover, until the moment of storing the magnitude of the duration of the current time interval, rewrite its previous value T _i-2 , which is also remembered, and then calculate the value $$\frac{\mathrm{one}}{T_i}$$

using expression (7), where T _i is the subsequent (future) duration of the time interval, i = 0, 1, 2, etc., while additionally multiplying the value $$\frac{\mathrm{one}}{T_i}$$

on A _i = A = const according to expression (1).

, определяющая величину изменяемого угла крена ракеты (в каждой четверти 0°-90°, 90°-180°, 180°-270° и 270°-360°) в течение временного интервала t_i. Для этого вычисленную величину $$A•\frac{1}{T_i}$$

интегрируют в течение временного интервала от 0 до t_i равного T_i. После чего процесс повторяют вновь.Since the values of T _i-1 and T _i-2 are stored, the calculated value is also stored $$A•\frac{\mathrm{one}}{T_i}$$

, which determines the magnitude of the variable roll angle of the rocket (in each quarter 0 ° -90 °, 90 ° -180 °, 180 ° -270 ° and 270 ° -360 °) during the time interval t _i . For this, the calculated value $$A•\frac{\mathrm{one}}{T_i}$$

integrate over a time interval from 0 to t _i equal to T _i . After which the process is repeated again.

Thus, the generated linearized signal on a rocket rotating in a roll angle, with a small change in the value of rocket acceleration during a 3/4 roll period, practically eliminates a change in the magnitude (magnitude) of the signal, leading to its non-symmetry with respect to zero.

The invention is illustrated by drawings:

Figures 1 and 2 show structural electrical circuits of a signal linearizer and a switched signal linearizer, respectively, based on this method, where: 1 is a roll sensor (DC), 2 is a roll signal shaper (FKS), 3 is a step signal shaper (FSS) , 4 - "RS" -trigger (PC), 5 - logical circuit "I" (I), 6a, 6b and 6c - first, second and third pulse shapers, respectively (FI1, FI2 and FI3), 7 - synchronizer ( C), 8 - pulse counter (SI), 9 - clock pulse shaper (FTI), 10 - shaper register (RSF), 11 - digital integrator (DI) H), 12 - calculator (B) for figures 1 and 12a, 12b - the first and second calculators, respectively (B1 and B2) for figure 2, 13 - register (WG), 14 - control unit (BU), 15 - commutator (K).

Figure 3 shows the waveform diagrams, which show: diagrams "a" and "b" - signals at the first and second outputs of the roll sensor 1, diagram "c" - the signal at the output of the roll signal shaper 2, diagrams "g", "d "and" e "are the signals at the outputs of, respectively, the first 6a, second 6b and third 6c of the pulse shapers, plot" g "is the signal at the non-inverted first output of the" RS "trigger 4, plot" z "is the signal at the output of the register shaper 10, plot "and" - signal at the output of register 13, plot "k" - signal at the output of calculator 12, plot "l" - signal (simplified in analog form) to ode digital integrator 11. Diagrams "h" and "i" conditionally shows the variation of magnitude signals U.

Figures 4 and 5 show structural and circuit diagrams of a digital integrator, respectively, for generating a roll angle signal on a rocket rotating in roll and its cells, where: 16a, 16b, ... 16n are the first, second, ... n-th digital cells (bits) of the integrator, respectively (Я1, Я2, ... Яn); 17 - two-input adder (CM _i ) and 18 - D-trigger (TT _i ) included in each digital cell, where i = 1, 2, ... n; (in this case, n = 4).

Figure 6 shows the waveform diagrams, as an example for the input four-digit binary parallel number 0011 (in decimal form 2 ¹ +2 ⁰ = 3), where: diagram "a" is the signal at the third inputs of digital cells 16, i.e. . at the clock inputs (C) of D-flip-flops 18 from cells 16a, ... 16n (with n =); diagrams "b ₁ ", "b ₂ ", "b ₃ " and "b ₄ " - signals at the first inputs of the first a ₁ , second a ₂ , third a ₃ and fourth a ₄ adders 17a, 17b, 17g and 17d, respectively those. from the junior (first) to the senior (fourth) categories; plot "c" is the signal at the second input b _{1 of the} adder 17a from the first digital cell 16a; diagrams "g ₁ ", "g ₂ ", "g ₃ " and "g ₄ " are the sum signals at the outputs of the first S ₁ , second S ₂ , third S ₃ and fourth S ₄ adders, respectively 18a, 18b, 18g and 18d; diagrams "d ₁ ", "d ₂ ", "d ₃ " and "d ₄ " - transfer signals at the inputs of the first from ₁ , second from ₂ , third from ₃ and fourth from ₄ adders, respectively 17a, 17b, 17g and 17d; diagrams e ₁ "," e ₂ "," e ₃ "and" e ₄ "are the signals at the transfer outputs of the first C ₂ , second C ₃ , third C ₄ and fourth C ₅ adders 17a, 17b, 17g and 17d, respectively; “g” - the signal at the outputs of the first 18a, second 18b, third 18c and fourth 18g of D-flip-flops (outputs 6 of digital cells 16), respectively, forming a four-digit binary number;

Figure 7 shows the plot of the signals when changing the angular velocity of rotation of the rocket, which presents: "h" is the signal at the input of zeroing (input R) of the digital integrator 11, "and" is the signal at the information input (inputs a _{i of the} adders) of the digital integrator 11 , “k” is the signal at the clock input (input C) of the digital integrator 11, “l” is the linearized signal at the output of the digital integrator 11.

In the signal linearizer (Fig. 1), the first (output 1) and second (output 2) outputs of the roll sensor 1 are connected to the corresponding inputs of the roll signal shaper 2, connected in series with the stepper signal shaper 3, the second output of which (output 2) is connected to the first information input (input 1) of the calculator 12. The integrator 11 is digital, the zeroing input (input R) of which is connected to the control inverted output of the “RS” trigger 4, which is the first output (output 1) of the step signal shaper. A clock shaper 9 is introduced into the signal linearizer, the output of which is connected to the clock input (input C) of the integrator, and its input is connected to the output of the synchronizer 7, which is the third output (output 3) of the step signal shaper, register 13 and calculator 12. At the same time the information input of the register is connected to the second output of the stepper signal former, and the information output of the register is connected to the second information (input 2) input of the calculator 12, the information output of which is connected to the information input digital integrator. The fourth output (output 4) of the stepper signal conditioner is connected to the recording input of the register 13. In this case, the fourth output of the step signal conditioner is the output of the first 6a pulse shaper, the input of which is connected to the output of the roll signal shaper 2.

In the switchable linearizer of the signal (figure 2), the first and second outputs of the roll sensor 1 are connected to the corresponding inputs of the roll signal shaper 2, connected in series with the stepper signal shaper 3. The integrator 11 is made digital, the zeroing input of which (input R) is connected to the invert output " RS "-trigger 4, which is the control of the first output (output 1) of the shaper of the stepped signal. The switchable signal linearizer includes: clock generator 9, two calculators the first 12a and second 12b, switch 15, register 13 and control unit 14. In this case, the second output (output 2) of the step signal generator is connected to the information input of the computer 12a, with the first information the input (input 1) of the second computer 12b and with the information input of the register 13.

The third output (output 3) of the step shaper is the output of the synchronizer 7, connected to the input of the clock shaper 9, the output of which is connected to the clock input (input C) of the digital integrator. The fourth output (output 4) of the step shaper is connected to the input of the register record, the information output of which is connected to the second information input (input 2) of the second calculator. The information output of the calculator is connected to the second information input (input 2) of the switch 15, the first information input (input 1) of which is connected to the information output of the first calculator. The information output of the switch is connected to the information input of the digital integrator. The control input of the switch is connected to the output of the control unit 14, the input of which is connected to the first output of the roll sensor 1. The fourth output of the step signal shaper is the output of the first 6a pulse shaper (not shown), the input of which is connected to the output of the roll signal shaper 2.

The step-by-step signal generator is made in the form of a synchronizer 7, a shaper register 10, an “I” logic circuit 5, a pulse counter 8, sequentially connected first 6a, second 6b and third 6c pulse shapers and an “RS” trigger 4, whose invertible output and register output shaper 10 are respectively the first (output 1) and second (output 2) outputs of the shaper of the step signal 3. The output of the synchronizer 7 and the first input of the logic circuit "And" 5 are the third output (output 3) of the shaper of the step signal, four the fourth output (output 4) of which is the first input of the “RS” trigger and the first output of the first pulse shaper.

The roll sensor 1 can be performed as a positional gyroscope ("Fundamentals of radio control" edited by Vejtsel V.A. and Tipugin V.N., Moscow, Sovetskoe Radio, 1973, pp. 49-52, Fig. 1.29), with In this case, the axes X _G and Y _G are interchanged, and instead of a mechanical potentiometer with a current collector, an optoelectronic one with two pairs of LED photodiodes separated by an opaque cylindrical surface with slots is used, with the center of the cylinder forming this surface connected to the axis of the frame, and two pairs of LEDs the photodiode is mounted on the gyroscope case.

In the shaper roll signal 2, which is a logical circuit "exclusive OR" and the logical circuit "AND" 5 can be used, for example, microcircuits, respectively 564LA7 and 564TM2. An “RS” trigger 4, for example, a serially connected “RS” trigger and an inverter.

The pulse shapers 6a, 6b, and 6c are waiting multivibrators, the first of which is triggered by the rise and fall edges of the input pulse signal, and the second and third by the fall edges.

The synchronizer 7 can be performed as, for example, a quartz oscillator of pulses. The pulse counter 8, registers 10 and 13 can be performed on microcircuits, respectively 564IE10 and 564IR6. The calculator 12, as well as the calculators 12a and 12b can be performed on the ROM, for example, on the chip 556RT7. The pulse generator 9 is a digital frequency divider.

The control unit 14 is designed as an “RS” trigger, the input “S” of which is connected to the output of the device generating a single pulse at the moment the on-board power supply (not shown) reaches the operating mode. At the R-input of the control unit connected to the first output of the roll sensor 1, the signal of which is shown on the diagram "a" of Fig. 3, pulses are generated from the rise front of this signal. Thus, an impulse is formed at the output of the control unit, which occurs before the start of rotation of the rocket along the roll angle, i.e. respectively, ωt = 0 °, and ends at the time corresponding to ωt = 180 °.

The switch 15 can be made as two identical electronic keys. The pulse signal from the output of the control unit 14 is fed directly to the control input of the first and through the inverter second electronic keys.

The adder 17 is a two-input adder, where 1 and 2 are the inputs of the summation, respectively, of the first a _i and second b _{i of the} number (one bit), c _i is the transfer input, C _{i + 1} is the transfer output, S _i is the sum. D-trigger 18, for example, 564TM2 chip.

The signal linearizer shown in figure 1, operates as follows. When the rocket rotates along the roll angle, the roll sensor 1 generates two signals that are 90 ° out of phase with respect to each other (plots "a" and "b" in figure 3). These two signals are respectively supplied to the first and second inputs of the roll signal shaper 2, at the output of which a signal is formed (diagrams “c” in FIG. 3). When this pulse signal arrives at the input of the step shaper 3, namely: at the input of the pulse shapers 6a, 6b and 6c connected in series, pulses delayed in time relative to each other will form at their outputs, respectively, diagrams "g", "d" and " e "(Fig.3).

At a point in time, for example, t _{-1, the} pulse from the output of the first pulse shaper 6a (diagram "g" of Fig. 3) is supplied to the first (input 1) of the "RS" -trigger 4 and sets the unit logic level to its inverted output (output 2) (figure 1). This output is the control output (output 1) of the shaper of the step signal 3, from which a single logic level is fed to the zeroing input (input R) of the digital integrator 11 and sets its output to zero.

On a non-inverted output (output 1) of the "RS" -trigger 4, the logic level is set to zero (plot "g" in figure 3). This level goes to the second (input 2) input of the logic circuit "And" 5 and prevents the signal from passing from the synchronizer 7 (coming to its first input 1) to the output of the logic circuit And 5. In this case, the pulses cease to go to the counting input (input C) pulse counter 8 and it from the counting mode of the number of pulses goes into the storage mode of this calculated number of pulses (binary number) corresponding to the value of the time interval T _-1 .

импульс, с выхода второго формирователя импульсов 6б (эпюра "д" на фиг.3) поступает на вход записи регистра формирователя 10 и записывает в него величину числа, соответствующего величине T_-1 (эпюра "з" на фиг.3) с выхода счетчика импульсов 8.At the same time, the same pulse at time t _-1 from the write output (output 4) of the stepper signal conditioner 3 goes to the recording input of the register 13 and writes information (in binary parallel code) into it, from the information second output (output 2) of the stepper signal conditioner 3, i.e. from the output of the register of the shaper 10 (plot "and" in figure 3), corresponding to the value of the interval T _-2 , which was previously recorded in the register of the shaper 10 by the pulse t _-2 (plot "d" in figure 3). At time $$t_{-\mathrm{one}}^{\text{'}\text{'}}$$

the pulse from the output of the second pulse shaper 6b (plot "d" in Fig. 3) is fed to the input of the register register of the shaper 10 and records the value of the number corresponding to the value T _-1 (plot "z" in Fig. 3) from the output of the counter pulses 8.

импульс с выхода третьего формирователя импульсов 6в (эпюра "е" на фиг.3) поступает на вход установки в нулевое состояние (вход R) счетчика импульсов 8 и устанавливает на его выходе логические нули.At time $$t_{-\mathrm{one}}^{"}$$

the pulse from the output of the third pulse shaper 6c (plot "e" in Fig. 3) is supplied to the zero input state (input R) of the pulse counter 8 and sets logical zeros at its output.

Similarly, the same pulse (plot “e” in FIG. 3) is fed to the input (input 2) of the “RS” trigger 4 and sets on its non-inverted (output 1) output a logical unit that allows passage through the first input of the logic circuit And 5 to its pulse output from the synchronizer 7 to the counting input (input C) of the pulse counter 8.

The numbers in the binary parallel code from the information output (output 2) of the stepper signal shaper 3 (shaper register 10) and the register output 13 are received, respectively, at the first (input 1) and second (input 2) information inputs of the calculator 12, which performs the calculation ( for example, when A ₀ = 1).

where T _and is the pulse repetition period at the output of the synchronizer 7, n is the number of these pulses in the interval T ₀ .

(эпюра "к" на фиг.3 в аналоговом виде) поступает на информационный вход цифрового интегратора 11. На тактируемый вход (вход С) цифрового интегратора подают тактовые импульсы с выхода формирователя тактовых импульсов 9, который уменьшает (делит) частоту повторения импульсов с выхода синхронизатора 7 формирователя ступенчатого сигнала (выход 3) в k раз, т.е. увеличивает их период повторения. Следовательно, за время интегрирования изменяемое от 0 до t₀ равное интервалу T₀, число тактовых импульсов (число дискретов) N в линеаризированном сигнале на выходе цифрового интегратора 11 будет равноThis is a binary number. $$\frac{\mathrm{one}}{n\cdot T_{\mathrm{and}}}$$

(plot "k" in figure 3 in analog form) is fed to the information input of the digital integrator 11. The clock pulse (input C) of the digital integrator serves clock pulses from the output of the pulse shaper 9, which reduces (divides) the pulse repetition rate from the output synchronizer 7 shaper step signal (output 3) k times, i.e. increases their repetition period. Therefore, during the integration time, varying from 0 to t ₀ equal to the interval T ₀ , the number of clock pulses (the number of samples) N in the linearized signal at the output of the digital integrator 11 will be equal to

Thus, since k = const, and n is directly proportional to the duration of T ₀ , the number of discrete N is also directly proportional to the duration of T ₀ , while the amplitude of the linearized signal A (plot "l" in figure 3) is equal to

those. the amplitude of the linearized signal A does not depend on the duration of the interval T ₀ .

, импульсом (с единичным логическим уровнем) с инвертированного (выход 2) выхода "RS"-триггера 4 (инвертированная эпюра "ж" на фиг.3), поступающим на вход обнуления цифрового интегратора 11, обнуляют его в течении $$t_{-1}-t_{-1}^{"}$$

(эпюра "л" на фиг.3, где приведена аналоговая форма сигнала).To exclude the formation of a false signal at the output of the digital integrator 11, in the interval of formation of the initial data for calculation $$\frac{\mathrm{one}}{{\mathrm{<figure-callout\; id="0"\; label="T"\; filenames="00000033.png"\; state="\{\{state\}\}">T</figure-callout>}}_0}$$

, a pulse (with a single logical level) from the inverted (output 2) output of the "RS" -trigger 4 (inverted plot "g" in Fig. 3), fed to the input of zeroing of the digital integrator 11, zero it during $$t_{-\mathrm{one}}-t_{-\mathrm{one}}^{"}$$

(plot "l" in figure 3, which shows the analog waveform).

As follows from the above, the delays introduced by the second 6b and third 6c pulse shapers, depicted respectively on the plots "e" and "e" in figure 3 are actually extremely small. And therefore, the pulse duration is small with a logic level of zero (plot "g" in figure 3).

. По этой величине дискретно в течение времени 0-t₁=T₁ цифровой интегратор 11 вновь построит линеаризированный сигнал с амплитудой A и т.д.After which the integration process is repeated again. In this case, similarly, from time t ₀ in the second register 13 will write information about the value of the duration T _-1 , and the shaper 10-T ₀ and the calculator 12 will calculate the value $$\frac{\mathrm{one}}{T_{\mathrm{one}}}=\frac{\mathrm{one}}{n\cdot T_{\mathrm{and}}}$$

. According to this value, digitally integrator 11 will again construct a linearized signal with amplitude A, etc., discretely over time 0-t ₁ = T ₁ .

As follows from the above at the initial time, for example, from 0 ° to 180 ° (plot "and" in Fig. 3), there is no information about the durations of the previous roll pulses at the input (inputs) of the calculator 12, and hence the linearized signal, which depicted by a dotted line (on the diagrams "h", "and", "k" and "l" of figure 3). Therefore, to eliminate errors in the formation of pulse-width modulated commands on a rocket rotating along a roll angle, for this period of time, for example, a delay is introduced to open the rudders or lock them in the middle position (if a delay in the start of control is acceptable), etc.

The switchable linearizer of the signal shown in figure 2 (excluding the delay), works similarly to that shown in figure 1 from the point in time corresponding to ω · t = 180 °.

At this point in time, the control unit 14 connects through an analog switch 15 to the information input of the digital integrator 11 a second calculator 12b. And up to this point in time it works similarly to that shown in figure 1, in the absence of register 13, i.e. only one previous value of the value of the interval T _i-1 . In this case, only the first calculator 12a is used, the signal from which passes through the first information input (input 1) of the analog switch 15 to the information input of the digital integrator 11.

The claimed integration method for forming a linearized signal on a rocket is implemented as follows. In the initial state, the output of the digital integrator sets the logic level to zero, i.e. output parallel binary number is zero. In addition, clock pulses are generated.

(эпюра "к" на фиг.3 в аналоговом виде). Для этого на первые входы a_i, соответствующих двухвходовых сумматоров цифрового интегратора подают значения каждого разряда (логические уровни единица или ноль) входного к-разрядного двоичного параллельного числа. Эти значения суммируют поразрядно в каждом последующем сумматоре по вторым входам b_i+1 с величинами разрядов двоичного параллельного числа с выходов переноса C_i+1 из каждого предыдущего сумматора. Например, на первый a_i, вход второго (i=2) сумматора поступает второй (старший) разряд входного двоичного параллельного числа, который суммируют (по второму входу b_i+1) со значением разряда переноса с выхода первого C_i+1 (i=1) сумматора, т.е. сумматора, на первый вход которого поступает младший (первый) разряд a_i входного двоичного параллельного числа.At the information input of the digital integrator 11, an input k-bit binary parallel number is input, for example, $$\frac{\mathrm{one}}{n\cdot T_{\mathrm{and}}}$$

(plot "k" in figure 3 in analog form). To this end, the first inputs a _i corresponding to the two-input adders of the digital integrator are supplied with the values of each bit (logical levels one or zero) of the input k-bit binary parallel number. These values are summed bitwise in each subsequent adder by the second inputs b _{i + 1} with the values of the bits of the binary parallel number from the transfer outputs C _{i + 1} from each previous adder. For example, on the first a _i , the input of the second (i = 2) adder receives the second (senior) bit of the input binary parallel number, which is summed (by the second input b _{i + 1} ) with the value of the transfer discharge from the output of the first C _{i + 1} (i = 1) adder, i.e. the adder, the first input of which receives the least (first) bit a _{i of the} input binary parallel number.

Moreover, each i-th D-flip-flop remembers the value of the discharge (logical level) S _{i of the} total parallel binary number from the output of each i-th two-input adder at the moments of formation of the rising edges of clock pulses. After passing through each rising edge of the clock pulses, the stored values of each bit of the binary parallel number are additionally summed over the transfer inputs c _i , with the corresponding bits from the previous total parallel binary number.

The duration of the integration interval is set corresponding to the duration of the angular interval equal to 90 ° (in each quarter of the roll period), at the end of which the logic level is set at the output of the integrator, and then the integration process is repeated again. At the same time, with each summation cycle, the current value of the output binary parallel number is increased by a constant discrete value, the digits of which form at the output of the integrator. The number of discrete values is limited to a predetermined value corresponding to the duration of the angular interval of 90 °, the discrete value is changed before the start of the integration process, in which the input k-bit binary parallel number is updated.

_,, являющимися входами сумматоров, формирующих разряды входного двоичного параллельного большего к-того, соединяют с корпусом, поскольку они являются незадействованными из-за отсутствия данных разрядов во входном к-разрядном двоичном параллельном числе.Moreover, the second input b ₁ _ minor (first) discharge (i = 1) of the first two-input adder (first cell) is connected to the housing, since it is unused due to the absence of the previous two-input adder. First entrances $$a\underset{\_}{{}_i}$$

_,, which are the inputs of the adders forming the bits of the input binary parallel greater than that, are connected to the housing, since they are unused due to the lack of these bits in the input k-bit binary parallel number.

The digital integrator 11 (Fig. 4), which implements the claimed integration method for generating a linearized signal on a rocket, contains "n" series-connected digital single-bit cells 16a, 16b, ... 16n, each of which includes a D-trigger 18 and a two-input adder 17. The zero-setting inputs (R inputs) of D-flip-flops from all digital single-bit cells 16a ... 16n are connected together and are the installation's input to the initial state of the integrator. The inputs of clock pulses (inputs C) of D-flip-flops from all one-bit cells are connected together and are the clock input of the integrator.

In each of the digital one-bit cell (Fig. 5), the output of the sum S _{i of the} adder 17 is connected to the information input (input D) of the D-flip-flop 18, the output of which is connected to the transfer input c _{i of the} adder 17. The transfer output C _{i + 1 of the} adder 17 from each previous digital single-bit cell 16a, 16b, ... 16n is connected to the second input b _{i + 1 of the} adder 17 from each subsequent digital single-bit cell.

The second adder input b ₁ from the first digital single-bit cell 16a and the first unused adder inputs from the last digital single-bit cells 16k1, ... 16n are connected to the housing.

Digital integrator 11 for generating a signal of the angle of heel on a roll rotating on a roll, shown in Fig.4, works as follows.

Information about the angle of heel of the rocket, presented in the form of a binary parallel number, is supplied to the first inputs of the corresponding digital cells 16a, 16b, ... 16k, i.e. to the first inputs a _{i of the} adders 17a, 17b, ... 17k, respectively.

Moreover, the least significant bit of the binary parallel number is fed to the first input of the first digital cell 16a, the second bit following it is fed to the first input of the second single-bit digital cell 16b, etc. up to the senior k-discharge, which is fed to the first input of a 16k digital single-bit cell.

In this case, for example, in the case of the presence of subsequent single-digit digital cells 16k1, ... 16n (not used at this input), their first inputs are connected to the housing. It should be noted that inactive digital cells of the highest order, which are not used at the first input, are required, if necessary, to increase the integration interval corresponding to an increase in the range (change in value) of the rocket angle signal, which eliminates the limitation of the linearized digital signal.

The second inputs b _{1 of the} adders 17b ... 17n receives pulse signals from the transfer output of the adder from the previous digital single-digit cell. In this case, the second input of the adder 17 from the first digital single-bit cell 16a is connected to the housing, because the previous cell is missing, and hence the transfer signal from its output. The third inputs (clock inputs C in FIG. 4) of all digital cells 16 are combined together and constant frequency clock pulses are fed to their inputs from the output of the clock generator 9 (diagram “a” in FIG. 6).

Previously, for example, at the moment the on-board power supply reaches the operating mode (if required), as well as at the moments of the end of the integration intervals, pulses are generated that are fed to the fourth inputs (zeroing inputs R) of all digital cells 16, combined together and installed on them outputs, namely the outputs of all D-flip-flops 18 (output 6) is a zero logic level.

As an example, the input signal of the digital integrator is represented by a two-bit parallel binary number 0011 in parallel form (in decimal code 3), for which the corresponding values of the logical levels a _i are shown (diagrams “b1”, “b2”, “b3” and “b4” on 6). Moreover, the location of the bits of the binary parallel four-digit number in Fig. 4 from left to right, i.e. from the youngest (MP) to the oldest (CP), it coincides with the membership of the bits of the first 16a, second 16b, third 16c and fourth 16g, respectively, in digital single-digit cells.

After zeroing, the adder 17a from the first cell 16a sums two signals at the input a ₁ - logical unit and at the input b ₁ - logical zero (diagrams "b _1" and "c" in Fig.6, respectively). At the same time, at the output S _{1 of the} adder 17a, a single logical level is formed (plot "g _1" in Fig.6). At the moment of arrival of the leading edge (increase) of the first clock pulse (plot “a” of FIG. 6), the unit logic level c of output S _{1 of} adder 17a along the D input of D-flip-flop 18a is assigned to its output, from which it goes to transfer input c ₁ the adder 17A (plot "d _1" Fig.6). At the output S _{1 of the} adder 17a, a zero logic level is generated, because S ₁ = 1 + 1 = 0 when transferring 1 to the output of C ₂ . The zero logic level c of output S _{1 is} supplied to the D input of the D-flip-flop 18a and the leading edge of the second clock pulse (diagram "a" of Fig. 6) is written to its output, from which it is transferred to the transfer input c _{1 of the} adder 17a. The process is then repeated.

Thus, in the first digital cell 16a at the output S _{1 of the} adder 17a, a signal is generated, the change in the logical levels of which are shown in the diagram "g _{1" of} Fig.6. Similarly, when the value of S ₁ (sum) is exceeded more than one, when the logic level 0 is formed at the output S ₁ , the output logic C ₂ will display a single logic level (diagram “d _{1” of} FIG. 6). As follows from this diagram, the logical levels zero and one correspond to the value of the binary number of the first (least significant bit) that determines the magnitude of the linearized signal.

The transfer signal (output 5) of the first digital cell 16a (signal C ₂ c of the output of the adder 17a) is supplied to the second input b _{2 of the} adder 17b from the second digital cell 16b, the first input of which ₂ receives the second (the next after the first least significant bit) bit input number (plot "b _2" in Fig.6), which is a single logical level. At the initial moment of time, at the output S _{2 of the} adder 17b from the second digital cell 16b, a single logical level is formed, because the zero and single logical levels are summed, while at the input of the transfer c ₂ is the zero logical level.

At the moment of arrival of the leading edge of the first clock pulse (plot “a” in FIG. 6), the unit logic level c of output S _{2 of} adder 17b at the D input of D-flip-flop 18b is registered at its output and fed to the transfer input c _{2 of} adder 17b. In this case, the transfer signal C ₂ c of the output of the adder 17a from the first digital cell 16a (diagram “e _1” in FIG. 6) is supplied to the second input b _{2 of the} adder 17b from the second digital cell 16b with a slight delay due to the time the signal passed through the two-input adder from the first digital cell. The transfer signal C ₂ changes its logic level from zero to unity at the second input b _{2 of the} adder (plot "e _1" in Fig.6). Therefore, at the output of S _{2 there} will remain a single logical level, and at the output of the transfer of C _{3, the} logical level will change from zero to one due to the transfer of a unit (plot “d _2” in Fig.6).

The leading edge of the second clock pulse (plot “a” in FIG. 6) goes to the D input of the D-flip-flop 18b and registers a single logic level from the output of the adder S ₂ at its output, i.e. leaves a single logical level at the input of the transfer c _{2 of the} adder 17b (plot "d _2" in Fig.6). The transfer signal C ₂ arrives at the second input b _{2 of the} adder 17b (plot "d _1" in Fig.6) similarly with a small delay, while at the output S _{2 of the} adder 17b a zero logic level is formed, and at its output of the transfer C _{3 the} unit logical level (plot "d _2" in Fig.6).

The leading edge of the third clock pulse (plot "a" in Fig.6) goes to the D input of the D-flip-flop 17b and registers at its output a logic level c of output S ₂ , which goes to the transfer input c _{2 of the} adder 17b. In this case, similarly, the second signal b _{2 of the} adder 17b receives the transfer signal C ₂ (plot "d _1" in Fig.6), which changes the logic level from zero to one and at the output S _{2 of the} adder forms a zero logic level, and the output of the transfer C _{3 will} remain a single logical level (plot "d _2" Fig.6).

Further, upon receipt of the leading edges of the fourth and subsequent clock pulses (plot "a" in Fig.6), the whole process for the second digital cell 16b is repeated.

The transfer signal (output 5) of the second digital cell 16b is supplied to the second input b _{3 of the} adder 17c from the third digital cell 16c. The first input a _{3 of the} adder 17c receives the third bit of the binary input number (plot "_3" in Fig.6), which represents a zero logic level. At the initial moment of time, at the output S _{3 of the} adder 17c from the third digital cell 16c, a zero logic level is formed, because two zero logic levels are summed.

At the moment of arrival of the leading edge of the first clock pulse (plot "a" in Fig. 6), the zero logic level from the output S _{3 of the} adder 17 along the D input of the D-flip-flop 18b is assigned to its output, and then it goes to the transfer input c _{3 of the} adder 17c. Moreover, similar to the above transfer signal C ₃ (a single logical level) at the second input b _{3 of the} adder 17B (plot "d _2" in Fig.6) will arrive with a slight delay. In this case, the output of S ₃ will change the zero logic level to one (plot "g _3" in Fig.6), and the output of the transfer C ₄ will remain a zero logic level (plot "d _3" in Fig.6).

The leading edge of the second clock pulse (plot "a" in Fig.6), arriving at the D input of the D-flip-flop 18b (plot "d _3" in Fig.6), registers a single logic level c of the output S _{3 of the} adder 17b, which goes to the transfer input from ₃ adders.

In this case, the unit logical level in the signal at the second input b _{3 of the} adder (diagram “d _2” in FIG. 6) does not change, and at the outputs S ₃ and C _{4 of the} adder zero and unit logic levels are formed (diagrams “g _3” and "D _3" in Fig.6, respectively).

The leading edge of the third clock pulse (plot "a" in Fig. 6) is fed to the D input of the D-flip-flop 18b, and the logic level is written from the output S _{3 of the} adder 17b to the output of the D-flip-flop 18b, which then goes to the transfer input c ₃ adder 17v. The second input b _{3 of the} adder 17c receives a signal from the transfer output C _{3 of the} adder 17b, in which the logical level changes from zero to one (plot "d _2" in Fig.6). At the output S _{3 of the} adder 17, a single logical level will be formed, and at the output of the transfer C ₄ , a zero logical level will be formed (plot “d _3” in Fig.6).

Similarly, the leading edges of the fourth and fifth clock pulses will form at the output S ₃ and the transfer output C _{4 of the} adder 17c the corresponding logic levels shown in Fig.6.

The transfer signal C ₄ from the output 5 of the third digital cell 16v is supplied to the second input b _{4 of the} adder 17 g from the fourth digital cell 16 g. At the first input a _{4 of the} adder 17g, the fourth (senior) bit of the binary input number (diagram "_4" in Fig.6) is received, which represents a zero logic level. At the initial moment of time, at the output S _{4 of the} adder 17g from the fourth digital cell 17g, a zero logic level is formed (two zero logic levels are summed).

At the time of the leading edge of the first clock pulse (plot "a" in Fig. 6), the zero logic level c of the output S _{4 of the} adder 17g at the D input of the D-flip-flop 18g is written to its output and goes to the transfer input c _{4 of the} adder 17. At the same time the transfer signal (zero logic level) at the second input b _{4 of the} adder 17g (plot "d _3" in Fig.6) will remain unchanged. The signals at the output of S ₄ and at the output of the transfer of C ₅ will also remain unchanged, i.e. zero logical levels (diagrams "g _4" and "d _4" in Fig.6).

At the moment of the arrival of the leading edge of the second clock pulse (plot “a” in FIG. 6), at the inputs of adder 17g there are zero logic levels of signals a ₄ and c ₄ and unit b ₄ , forming a single logic level at its output S ₄ (plot “g” _{4 ”} in FIG. 4). The leading edge of the second clock pulse, arriving at the D input of the D-flip-flop 18g, registers a single logic level at its output, which goes to the transfer input from ₄ adders 17g.

In this case, the unit logical level in the signal at the second input b _{4 of the} adder 17 g (diagram "d _3" in Fig.6) will change its logic level from zero to unit and at the outputs S ₄ and C _{5 of the} adder 17 g the corresponding logic and zero levels will be formed (plot "g _4" and "d _4" in Fig.6, respectively).

The leading edge of the third clock pulse (plot “a” in FIG. 6) enters the D input of the D-flip-flop 18g and registers from the output S _{4 of the} adder 17g to the output of the D-flip-flop a single logic level (saves the previous one), which goes to the transfer input c ₄ adders 17g.

At the same time, at the second input b _{4 of the} adder 17g, the logical level c changes from unity to zero (plot "d _3" in Fig.6) and at the output S _{4 of the} adder 17g a single logic level is formed, and at the output of the transfer C _{5 the} logic level is preserved ( plot "d _4" in Fig.6).

The leading edge of the fourth clock pulse goes to the D input of the D-flip-flop 18g and registers from the output S _{4 of the} adder 17g to the output of the D-flip-flop a single logic level, which goes to the transfer input from ₄ adders 17g (previous logical levels are stored at the outputs S _{4 of the} adder and D-trigger).

At the same time, at the second input b _{4 of the} adder 17g, the logical level will change from zero to one (plot "d _3" in Fig.6), and at the outputs S ₄ and transfer C _{5 of the} adder 17g, the previous single logic levels will be saved (plots "b _4" and "d _4" in Fig.6, respectively).

The leading edge of the fifth clock pulse goes to the D input of the D-flip-flop 18g and registers from the output S _{4 of the} adder 17g to the output of the D-flip-flop a single logic level, which goes to the transfer input from ₄ adders 17g (the previous logical level is saved). At the same time, at the second input b _{4 of the} adder 17g, a single logical level will be saved (plot “d _3” in FIG. 6), and at the output S _{4 of the} adder 17g the logical level will change from one to zero, and the previous logical unit will be saved at the transfer output C ₅ level (plots "b _4" and "d _4" in Fig.6, respectively).

At the moment of arrival, for example, of the leading edge of the sixth pulse, a zeroing pulse is formed from it, which arrives at the R inputs of the digital cells and sets the logic level at their outputs. Then the integration process is repeated again.

Thus, in the process of integration when changing the number of clock pulses from zero to five, the binary number at the outputs of the adder transfer from each digital cell increases. In this case, a binary number is formed in a parallel form, increasing with each clock pulse by the value of the input number in this case, by a value of 11 in the binary code. According to Fig. 6, the initial state of the integrator is 0000, at the moment of arrival of the first clock pulse - 1100, of the second - 0110, of the third - 1001, of the fourth - 0011 and at the moment of arrival of the fifth clock pulse, taking into account the transfer signal c ₄ in the fourth cell 1d - 1111.

Therefore, the maximum signal at the output of the four-digit digital integrator in this case is 1111 (15 = 3 · 5 in the decimal code), which corresponds to the plot "g" in Fig.6. As follows from the above, the input signal (in binary parallel code) is two single logic levels that go to the second inputs a _1, a ₁ and a _2, respectively, of the first and second digital one-bit cells, and the inputs a ₃ and a _4, as well as the second input b ₁ connected to the housing, while the output signal (its discharge) is removed from the sixth outputs of all four digital one-bit cells.

In some cases, for example, when it is impossible to lower the frequency of clock pulses, when the parallel binary number has an excessive number of bits, the lower output bits are not used, which is shown in Fig.4.

соответствует величине дискрета ΔA₀ в интервале T₀, а при уменьшении угловой скорости вращения ракеты по углу крена, т.е. при T₁>T₀ в следующем интервале интегрирования T₁ соответствует величине дискрета ΔA₁<ΔA₀ (эпюра "и" на фиг.7 в аналоговом виде). При этом обнуление цифрового интегратора 11 осуществляют импульсами, приведенными на эпюре "з" фиг.7 (импульсы со второго выхода "RS"-триггера 4). Каждый фронт нарастания тактовых импульсов (эпюра "к" на фиг.7) c выхода формирователя тактовых импульсов 9 увеличивает величину интегрированного сигнала на величину дискрета соответственно ΔA₀ или ΔA₁ (эпюра "л" на фиг.7).In the general case, as follows from the above, an input k-bit binary parallel number, for example, $$\frac{\mathrm{one}}{n\cdot T_{\mathrm{and}}}$$

corresponds to the discrete value ΔA ₀ in the interval T ₀ , and when the angular velocity of rotation of the rocket decreases along the angle of heel, i.e. when T ₁ > T ₀ in the next integration interval T ₁ corresponds to the discrete value ΔA ₁ <ΔA ₀ (plot "and" in Fig.7 in analog form). In this case, the zeroing of the digital integrator 11 is carried out by the pulses shown in the diagram "h" of Fig. 7 (pulses from the second output of the "RS" -trigger 4). Each rise front of clock pulses (plot "k" in Fig. 7) from the output of the pulse shaper 9 increases the value of the integrated signal by the discrete value ΔA ₀ or ΔA _1, respectively (plot "l" in Fig. 7).

Thus, each clock pulse (its rise front) sums (on the adders) the binary number ΔA ₀ in a parallel code with the number stored in the cells (D triggers): first with zero, then with ΔA ₀ , 2ΔA ₀ , 3ΔA ₀ and t .d. until the digital integrator 11 is reset. Then the process is repeated again for ΔA ₁ (plot "l" in Fig.7), etc. As follows from the above, the discrete value ΔA _{i is} inversely proportional to the value of T _i , and the number of discretes is directly proportional to T _i . In this case, the minimum number of discretes corresponds to the maximum speed of the rocket. This should be taken into account to avoid a decrease in accuracy due to a decrease in the number of discrete samples in the linearized signal, which is eliminated by a corresponding increase in the frequency of the clock signal, and hence the number of cells.

In the description, in order to simplify and facilitate understanding of the operation of the claimed technical solution, some signal diagrams are given in analog form.

Therefore, the proposed group of inventions, a method of generating a linearized signal on a roll rotating in a roll angle, a signal linearizer, a switchable signal linearizer, an integration method for generating a linearized signal on a rocket and a digital integrator for its implementation improves the accuracy of forming a linearized signal on a roll rotating in roll angle, by eliminating or reducing the change in the magnitude (amplitude) of the linearized signal during acceleration or deceleration missile.

Claims (11)

1. A method of generating a linearized signal on a rocket rotating in roll angle, comprising generating a roll angle of pulses mounted on the rocket sensor, in which the rocket rotation period in roll angle is divided into time intervals corresponding to one quarter of the roll period, measuring and storing the duration of the current time interval T _i-1 , characterized in that until the moment of storing the value of the duration of the current time interval, its previous value T _i-2 , which is also remembered, is rewritten, you calculate the value $$\frac{\mathrm{one}}{T_i}$$

using the expression $$\frac{\mathrm{one}}{T_i}=\frac{2}{T_{i-\mathrm{one}}}-\frac{\mathrm{one}}{T_{i-2}}$$

, where T _i - the subsequent duration of the time interval, i = 0, 1, 2, etc., while calculating the value $$\frac{\mathrm{one}}{T_i}$$

additionally multiplied by A = const - the given value of the amplitude of the linearized signal, and during the change in the time interval from 0 to t _i corresponding to the value of the angular interval equal to a quarter of the roll period of rocket rotation, the value $$A•\frac{\mathrm{one}}{T_i}$$

integrate, after which the process is repeated again. 2. A signal linearizer comprising an integrator, a calculator, a roll signal shaper and a step signal shaper, a roll sensor, the first and second outputs of which are connected to the corresponding inputs of a roll signal shaper, characterized in that a register and a clock pulse shaper are introduced into it, and the integrator is digital, while the input of the pulse shaper is connected to the third output of the shaper of the step signal, and the output is connected to the clock input of the integrator, the register entry input is connected to the fourth output of the step signal former, the information output of the register is connected to the second information input of the calculator, and its information input together with the first information input of the calculator is connected to the second output of the step signal shaper, the information output of the calculator is connected to the information input of the integrator, zeroing input which is connected to the first being the control output of the stepper signal conditioner. 3. The signal linearizer according to claim 2, characterized in that, the pulse shaper is designed as a digital frequency divider. 4. The signal linearizer, according to claim 2, characterized in that the step-by-step signal shaper is made in the form of a synchronizer, a shaper register, an "AND" pulse counter logic circuit, sequentially connected first, second and third pulse shapers, an "RS" trigger, when In this case, the invertible output of the “RS” trigger and the output of the shaper register are the first and second outputs of the step signal shaper, the synchronizer output and the first input of the logic circuit “And” are the third output of the step shaper signal, fourth output of which is the first input terminal "RS" -triggera and the first output of the first pulse shaper. 5. A switchable signal linearizer comprising an integrator, a calculator, a roll signal shaper and a step signal shaper, a roll sensor, the first and second outputs of which are connected to the corresponding inputs of the roll signal shaper, characterized in that a register, a control unit, a switch are inserted into it , the second calculator and generator of clock pulses, and the integrator is made digital, while the input of the generator of clock pulses is connected to the third output of the generator I step signal, and the output is with the clock input of the integrator, the first information input of the second calculator and the information input of the register together with the information input of the first calculator are connected to the second output of the step signal generator, the information output of the register is connected to the second information input of the second calculator, the information output of which is connected with the second information input of the switch, the first information input of which is connected to the information output of the first computer, information The output of the switch is connected to the information input of the integrator, and the control input of the switch is connected to the output of the control unit, the input of which is connected to the first output of the roll sensor, the input of the register record is connected to the fourth output of the step signal shaper, the first output of which is connected to the integrator zeroing input. 6. The switchable linearizer of the signal according to claim 5, characterized in that the pulse shaper is designed as a digital frequency divider. 7. The switchable signal linearizer according to claim 5, characterized in that the step-by-step signal shaper is made in the form of a synchronizer, a shaper register, an “I” logic circuit, a pulse counter, sequentially connected first, second and third pulse shapers, an “RS” trigger while the invertible output of the "RS" -trigger and the output of the shaper register are the first and second outputs of the stepper signal shaper, the synchronizer output and the first input of the logic circuit "And" are the third output of the shaper step signal, the fourth output of which is the first input of the "RS" -trigger and the first output of the first pulse shaper. 8. The switchable linearizer according to claim 5, characterized in that the control unit is designed as an “RS” trigger, the R-input of which is connected to the first output of the roll sensor, and the S-input is connected to the output of the onboard power source. 9. The switchable linearizer according to claim 5, characterized in that the switch is made as two identical electronic keys. 10. An integration method for generating a linearized signal on a rocket rotating in an angle of roll, which consists in integrating the amplitude of the clock pulses in a time interval equal to the duration of the angular interval, setting the logic level to zero at the outputs of the D triggers and entering parallel bit binary number at the inputs of adders, characterized in that the first inputs of the adders fed a _i corresponding to the value of each bit of the input to the parallel-bit binary numbers, to torye bitwise summed in each subsequent respective adder on a second of its inputs b _{i + 1} with the values of bits of the binary parallel number with C _{i + 1} transfer outputs of each of the previous adder, stored value of the total of the parallel binary number at the output the sum S _i, corresponding to each adder in forming the first moment of the rising edge of clock pulses, and after further stored summed values of each bit of the parallel binary number input to the transfer of data inputs c _i sum Ator, the values of sums of the first input a _i with the second b _i, where i = 1, 2, ... k - number of bits of the binary parallel number (from least to most), then the summation cycle is repeated many times at the moments of forming the second and subsequent fronts increase of clock pulses, and the duration of the integration interval is set corresponding to the duration of the angular interval, equal to 90 °, at the end of which the logic level is set at the outputs of the D-flip-flops, and then the integration process is repeated again, etc. What is the meaning of the current value of the binary binary output number, the bits of which are formed at the outputs of the D-flip-flops, with each summation cycle, they increase by a constant discrete amplitude, the number of discrete quantities of which is limited by a predetermined value corresponding to the duration of the angular interval, the discrete value is changed before the start of the integration process, at which update the input to-bit binary parallel number. 11. A digital integrator containing "n" series-connected digital one-bit cells, each of which includes a D-trigger, an adder, characterized in that the adder is a two-input, the sum output of which is connected to the information input of the D-trigger, the information output of which is from the cell is connected to the information input from the previous cell, the output of the D-trigger is connected to the adder transfer input, which from each previous digital one-bit cell is connected to the second adder input from each subsequent digital single-bit cell, the first adder inputs from all digital single-bit cells connected together and are the information input of the digital integrator, the second adder input from the first digital single-bit cell and the first adder input from the last single-bit cell are not borrowed and connected to the housing, and the outputs D- triggers from the corresponding cells are combined and are the output of a digital integrator.

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