RU2515543C1 - High-speed differential link driver - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: method is realised by a high-speed differential link driver, having first and second input anti-phase voltage sources connected to corresponding inputs of first and second output stages, first and second load capacitors connected to corresponding outputs of the first and second output stages, the output of the first output stage, the input of a first non-inverting voltage repeater, the current output of a first non-inverting current repeater, a first additional capacitor and a second additional capacitor.

EFFECT: faster operation of the driver when operating on a capacitive load owing to elimination of the effect of the first and second capacitors of the load circuit on the transient process.

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Description

The invention relates to the field of radio engineering and communications and can be used as a device for amplifying and converting analog signals in the structure of “systems on a chip” and “systems in a housing” for various functional purposes (for example, operational amplifiers operating on a capacitive load).

Known driver circuitry for communication lines built on the basis of negative feedback operational amplifiers, which became the basis of many serial microcircuits of the first and second generation [1-7].

The closest prototype (figure 1) of the claimed device is a differential communication line driver described in patent application US 2006/0202753, containing the first 1 and second 2 sources of input antiphase voltages associated with the corresponding inputs of the first 3 and second 4 output stages, the first 5 and second 6 load capacitors connected to the corresponding outputs 7 and 8 of the first 3 and second 4 output stages. Capacitors 5 and 6 model the capacitive component of the load circuit, for example, the capacitance of a differential communication line.

A significant drawback of the known driver is that it is characterized by a relatively low speed due to the influence on the transient of the first 5 and second 6 capacitors of the load circuit.

The main objective of the invention is to increase the speed of the driver when working on capacitive load, expanding the range of its operating frequencies.

The problem is achieved in that in the driver of the differential communication line (Fig. 1), containing the first 1 and second 2 sources of input antiphase voltages associated with the corresponding inputs of the first 3 and second 4 output stages, the first 5 and second 6 load capacitors connected to corresponding outputs 7 and 8 of the first 3 and second 4 output stages, new elements and connections are provided - output 7 of the first 3 output stage is connected to the input of the first 9 non-inverting voltage follower and the current output of the first 10 inverters the current repeater, the output 8 of the second 4 output stage is connected to the input of the second 11 non-inverting voltage follower and the current output of the second 12 inverting current follower, and between the output of the first 9 non-inverting voltage follower and the input of the second 12 inverting current follower, the first 13 additional capacitor is connected, and between the output of the second 11 non-inverting voltage follower and the input of the first 10 inverting current follower included the second 14 additional capacitor.

Figure 1 shows a diagram of the driver of the prototype.

Figure 2 shows a diagram of the inventive device in accordance with the claims.

Figure 3 presents a computer model of the circuit of the inventive device of figure 2 in the environment of PSpice, on which, in accordance with the specifics of the interface PSpice, the following notation of the elements corresponding to _figure 2: R1 = R _out.3 (16), R2 = R _{output 4} (18), C _p1 = C5, C _p2 = C6, C _k1 = C13, C _k2 = C14, F2 - current amplifier 12, F3 - current amplifier 10. Non-inverting voltage followers marked with the symbol “1” correspond to non-inverting repeaters 9 and 11 of the circuit of figure 2.

Figure 4 shows the dependence of the voltage settling time (t _mouth ) at the output 7 of the first 3 output stage of the driver on the capacitance value of additional capacitors 13 and 14 (C _k1 = C13, C _k2 = C14).

Figure 5 shows the dependence of the time to establish the voltage at the output 8 of the second 4 output stage of the driver on the capacitance value of the additional capacitors 13 and 14 (C _k1 = C13, C _k2 = C14).

From the graphs of figure 4, figure 5 shows that with the introduction of the first 13 and second 14 additional capacitors, the time to establish the output pulses of the driver decreases more than 20 times. The closer the value of the capacitance C _to = C13 = C14 to the capacitance C _n = C6 = C5, the less t _mouth .

The high-speed driver of the differential communication line contains the first 1 and second 2 sources of input antiphase voltages associated with the corresponding inputs of the first 3 and second 4 output stages, the first 5 and second 6 load capacitors connected to the corresponding outputs 7 and 8 of the first 3 and second 4 output stages . The output 7 of the first 3 output stage is connected to the input of the first 9 non-inverting voltage follower and the current output of the first 10 inverting current follower, the output 8 of the second 4 output stage is connected to the input of the second 11 non-inverting voltage follower and the current output of the second 12 inverting current follower, between the output of the first 9 non-inverting voltage follower and the input of the second 12 inverting current followers included the first 13 additional capacitor, and between the output of the second 11 non-inverting a voltage follower and the input of the first 10 inverting current followers included the second 14 additional capacitor.

Consider the work of the known (figure 1) and the proposed (figure 2) devices.

When an abrupt positive change in the input voltage at the input of the first 3 output stage of Fig. 1 and a negative change in the input voltage at the input of the second 4 output stage begins the process of charging the first 5 capacitor of the load circuit (C5) and the discharge of the second 6 capacitor of the load circuit (C6). In this case, the time constants of the charge and discharge circuits are determined by the output resistances of the first 3 output stage (R _{o 3} ) and the capacity of the first 5 load capacitor (C5), as well as the output resistance of the second 4 output stage (R _{o 4} ) and the capacity of the second 6 capacitor load (C6). Ultimately, these time constants have a negative impact on the performance of the prototype driver, in which the transition time for many practical cases is unacceptably long.

In the claimed circuit of FIG. 2, the voltage at the first 5 load capacitor C5 is transmitted to the output of a non-inverting voltage amplifier 9, which creates a current through the first 13 additional capacitor. As a result, a correcting current pulse is generated at the output of the inverting current amplifier 12, which contributes to a faster discharge of the capacitor 6 (C6). This is evidenced by the graphs of Fig. 5, when at C _to ≈C13 = 19.9 pF the time of establishment of the transition process decreases from 30 ns to 1.3 ns, i.e. more than 20 times.

Similarly, the voltage reduction at the second 6 load capacitor (C6) is transmitted to the output of the non-inverting voltage amplifier 11, which creates a current through the second 14 additional capacitor. As a result, a correcting current pulse is generated at the output of the inverting current amplifier 10, which contributes to a faster charge of the capacitor 5. This is evidenced by the graphs of Fig. 5, when at C _to ≈С13 = 19.9 pF the transition process settling time decreases from 30 ns to 1 3 ns, i.e. more than 20 times.

Thus, the inventive driver provides with capacitive load higher speed.

BIBLIOGRAPHIC LIST

1. Patent US 3769605, fig. 2.

2. Patent US 7863977, fig. 1.

3. Patent US 5345471, fig. 1B.

4. Patent US 7327189, fig. 7.

5. Patent application US 2001/0050333, fig. 3.

6. Patent application US 2003/0137345, fig.2.

7. Patent US 6222416.

8. Patent US 5557238, fig. 1.

9. Patent application US 2011/0158435, fig. 1.

10. Patent application US 2010/0259323, fig. 2.

11. Patent US 6741132, fig. 4.

12. Patent application US 2011/0227652, fig. 2.

13. Patent application US 2009/0045876, fig.1a.

Claims (1)

A high-speed differential line driver containing the first (1) and second (2) input phase-voltage sources associated with the corresponding inputs of the first (3) and second (4) output stages, the first (5) and second (6) load capacitors connected to the corresponding outputs (7) and (8) of the first (3) and second (4) output stages, characterized in that the output (7) of the first (3) output stage is connected to the input of the first (9) non-inverting voltage follower and the current output of the first (10) inverting current repeater output (8) the second (4) output stage is connected to the input of the second (11) non-inverting voltage follower and the current output of the second (12) inverting current follower, and between the output of the first (9) non-inverting voltage follower and the input of the second (12) inverting current follower ) an additional capacitor, and between the output of the second (11) non-inverting voltage follower and the input of the first (10) inverting current follower, a second (14) additional capacitor is connected.

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