CN103543781A

CN103543781A - Low-dropout linear regulator

Info

Publication number: CN103543781A
Application number: CN201310521445.XA
Authority: CN
Inventors: 贾雪绒
Original assignee: Xian Sinochip Semiconductors Co Ltd
Current assignee: Xian Unilc Semiconductors Co Ltd
Priority date: 2013-10-29
Filing date: 2013-10-29
Publication date: 2014-01-29
Anticipated expiration: 2033-10-29
Also published as: CN103543781B

Abstract

The invention provides a low-dropout linear regulator which comprises a linear regulator body, a first P-channel metal oxide semiconductor (PMOS) tube, a second PMOS tube, a first N-channel metal oxide semiconductor (NMOS) tube, a second NMOS tube, a first capacitor, a second capacitor and an inverting amplifier. A drain electrode of the first PMOS tube is connected with a source electrode of the second PMOS tube, a source electrode of the first PMOS tube is connected with the linear regulator body, and the drain electrode and the source electrode of the first PMOS tube are connected through the second capacitor. A drain electrode of the second PMOS tube is connected with a drain electrode of the first NMOS tube, a source electrode of the first NMOS tube is connected with a drain electrode of the second NMOS tube, a source electrode and the drain electrode of the second NMOS tube are connected through the first capacitor, and the source electrode of the NMOS tube is grounded. The input end of the inverting amplifier is respectively connected with a grid electrode of the second PMOS tube and a grid electrode of the first NMOS tube, and the output end of the inverting amplifier is respectively connected with a grid electrode of the first PMOS tube and a grid electrode of the second NMOS tube. The low-dropout linear regulator can effectively reduce voltage fluctuation of output voltage.

Description

A kind of low pressure difference linear voltage regulator

Technical field

The present invention relates to a kind of voltage stabilizer, be specifically related to a kind of low pressure difference linear voltage regulator.

Background technology

Along with the continuous upgrading of JEDEC interface standard, the clock frequency of DRAM constantly raises.The electric current that DRAM internal logic circuit consumes is also in continuous increase.DRAM technology characteristics size constantly reduces simultaneously, and chip area is also in constantly compressing, and this has just proposed challenge to the design of the linear voltage regulator for power logic circuitry in DRAM.Linear voltage regulator used in current DRAM is in order to reach the less target of voltage fluctuation, the quiescent dissipations that many employings increase voltage stabilizer self amplifier improve the reaction velocity of linear voltage stabilization itself, or the interior electric capacity of sheet on increase linear stabilizer output voltage network is to reduce the fluctuation of voltage.

For example, in the low-voltage-drop linear voltage regulator of the Quick-return that the patent No. is 200510064624.0, mention by detecting the size of output current, the bias current of adjusting second level amplifier is accelerated the reply of linear voltage regulator.The drawback of this way is: when output current is larger, the quiescent dissipation of second level amplifier can increase, and increases the whole quiescent dissipation that increases linear voltage regulator, and the extra current detection circuit of introducing, the complicacy that has increased design, has taken extra area.

Summary of the invention

The object of the invention is to overcome the shortcoming of above-mentioned prior art, a kind of low pressure difference linear voltage regulator of the present invention, the voltage fluctuation of output voltage when this voltage stabilizer effectively reduces load current increase or reduces.

For achieving the above object, low pressure difference linear voltage regulator of the present invention comprises linear voltage regulator, a PMOS pipe, the 2nd PMOS pipe, a NMOS pipe, the 2nd NMOS pipe, the first electric capacity, the second electric capacity and polarity-inverting amplifier;

The drain electrode of a described PMOS pipe is connected with the source electrode of the 2nd PMOS pipe respectively, the source electrode of the one PMOS pipe is connected with linear voltage regulator, between the drain electrode of the one PMOS pipe and source electrode, by the second electric capacity, be connected, the drain electrode of the 2nd PMOS pipe is connected with the drain electrode of a NMOS pipe, the source electrode of the one NMOS pipe is connected with the drain electrode of the 2nd NMOS pipe, the source electrode of the 2nd NMOS pipe with drain electrode between by the first electric capacity, be connected, the source ground of the 2nd NMOS pipe;

The input end of described polarity-inverting amplifier is connected with the grid of the 2nd PMOS pipe, the grid of a NMOS pipe respectively, and the output terminal of polarity-inverting amplifier is connected with the grid of a PMOS pipe, the grid of the 2nd NMOS pipe respectively.

Described linear voltage regulator comprises input port, output port, operational amplifier, the 3rd PMOS pipe, the first resistance, the second resistance, the 3rd electric capacity and constant current source;

The reverse input end of described operational amplifier is connected with input port, the output terminal of operational amplifier is connected with the grid of the 3rd PMOS pipe, the source electrode of the 3rd PMOS pipe is connected with the source electrode of a PMOS pipe, the drain electrode of the 3rd PMOS pipe respectively with the in-phase input end of operational amplifier, one end of the first resistance, one end of the second resistance, the input end of constant current source and output port be connected, the other end ground connection of the first resistance, ground connection after the other end of the second resistance is connected with the 3rd capacitances in series, the output head grounding of constant current source.

While being switched to zero when the voltage of the voltage of described first electric capacity one end and second electric capacity one end is switched to high level from zero or from high level, the voltage of the voltage of the first electric capacity other end and the second electric capacity other end can dynamically be drawn high or be dragged down, and causes the output current of the 3rd PMOS pipe to make corresponding response.

The present invention has following beneficial effect:

The switching that low pressure difference linear voltage regulator of the present invention grows out of nothing along with load current, in linear voltage regulator, the grid of the 3rd PMOS is because the first electric capacity and the second electric capacity have been coupled to the pulse of a negative sense, cause the grid terminal voltage transient state of its 3rd PMOS pipe to reduce, the output current of the 3rd PMOS increases, linear voltage regulator is made reaction fast for the variation of load current, makes the drop-down amplitude of output voltage less, along with load current is from there being the switching to nothing, the grid end of the 3rd PMOS in linear voltage regulator has been coupled to the pulse of a forward, cause the grid voltage of the 3rd PMOS pipe to be drawn high by transient state, the output current of the 3rd PMOS pipe reduces, linear voltage regulator is also made reaction fast for the minimizing of load current, make the upper tentering degree of output voltage less, thereby make under the prerequisite of linear voltage regulator without extra increase quiescent dissipation, realize rapid reaction, simultaneously in the situation that keeping output capacitance constant, no matter be on voltage, be pulled through in journey or voltage downdraw process in all can reduce the voltage wave of output voltage.

Accompanying drawing explanation

Fig. 1 is circuit diagram of the present invention;

Fig. 2 is the transient waveform figure of the output voltage of downdraw process neutral line voltage stabilizer in the present invention;

Fig. 3 is the transient waveform figure that is pulled through the output voltage of journey neutral line voltage stabilizer in the present invention.

Embodiment

Below in conjunction with accompanying drawing, the present invention is described in further detail:

With reference to figure 2, low pressure difference linear voltage regulator of the present invention, comprises linear voltage regulator, a PMOS pipe T1, the 2nd PMOS pipe T2, a NMOS pipe T3, the 2nd NMOS pipe T4, the first capacitor C 1, the second capacitor C 2 and polarity-inverting amplifier U1; The drain electrode of a described PMOS pipe T1 is connected with the source electrode of the 2nd PMOS pipe T2 respectively, the source electrode of the one PMOS pipe T1 is connected with linear voltage regulator, between the drain electrode of the one PMOS pipe T1 and source electrode, by the second capacitor C 2, be connected, the drain electrode of the 2nd PMOS pipe T2 is connected with the drain electrode of a NMOS pipe T3, the source electrode of the one NMOS pipe T3 is connected with the drain electrode of the 2nd NMOS pipe T4, between the source electrode of the 2nd NMOS pipe T4 and drain electrode, by the first capacitor C 1, be connected, the 2nd NMOS manages the source ground of T4; The input end of described polarity-inverting amplifier U1 is connected with the grid of the 2nd PMOS pipe T2, the grid of a NMOS pipe T3 respectively, and the output terminal of polarity-inverting amplifier U1 is connected with the grid of a PMOS pipe T1, the grid of the 2nd NMOS pipe T4 respectively.While being switched to zero when the voltage of the voltage of described first capacitor C 1 one end and second capacitor C 2 one end is switched to high level from zero or from high level, the voltage of the voltage of first capacitor C 1 other end and second capacitor C 2 other ends can dynamically be drawn high or be dragged down, and cause the output current of the 3rd PMOS pipe T5 to make corresponding response, improve the reaction velocity of linear voltage regulator.

Described linear voltage regulator comprises input port, output port, operational amplifier, the 3rd PMOS pipe T5, the first resistance R 1, the second resistance R 2, the 3rd capacitor C 3 and constant current source; The reverse input end of described operational amplifier is connected with input port, the output terminal of operational amplifier is connected with the grid of the 3rd PMOS pipe T5, the source electrode of the 3rd PMOS pipe T5 is connected with the source electrode of a PMOS pipe T1, the drain electrode of the 3rd PMOS pipe T5 respectively with the in-phase input end of operational amplifier, one end of the first resistance R 1, second one end of resistance R 2, the input end of constant current source and output port be connected, the other end ground connection of the first resistance R 1, the other end of the second resistance R 2 and the 3rd capacitor C 3 are connected in series rear ground connection, the output head grounding of constant current source.

With reference to figure 2 and Fig. 3, in Fig. 2, curve a is novel linear voltage stabilizer, be less than 1ns turnaround time, curve b is traditional linear voltage regulator, be greater than 6ns turnaround time, in Fig. 3, curve c is novel linear voltage stabilizer, be less than 1ns turnaround time, curve d is traditional linear voltage regulator, be greater than 6ns turnaround time, the load current of low pressure difference linear voltage regulator neutral line voltage stabilizer of the present invention grows out of nothing and switches, in linear voltage regulator, the grid of the 3rd PMOS pipe T5 is because the first capacitor C 1 and the second capacitor C 2 are connected with the output terminal of polarity-inverting amplifier U1, cause the grid voltage transient state of the 3rd PMOS pipe T5 to reduce, the output current of the 3rd PMOS pipe T5 increases, linear voltage regulator is made reaction fast for the variation of load current, in same load capacitance situation, the drop-down amplitude of output voltage is less.Along with load current is from there being the switching to nothing, in linear voltage regulator, the grid of the 3rd PMOS pipe T5 is because the first capacitor C 1 and the second capacitor C 2 are directly connected with the input end of polarity-inverting amplifier U1, thereby cause the grid voltage of the 3rd PMOS pipe T5 to be drawn high by transient state, the output current of the 3rd PMOS pipe T5 reduces, linear voltage regulator is also made reaction fast for the minimizing of load current, and the upper tentering degree of output voltage is less.

Claims

1. a low pressure difference linear voltage regulator, it is characterized in that, comprise linear voltage regulator, a PMOS pipe (T1), the 2nd PMOS pipe (T2), a NMOS pipe (T3), the 2nd NMOS pipe (T4), the first electric capacity (C1), the second electric capacity (C2) and polarity-inverting amplifier (U1);

The drain electrode of a described PMOS pipe (T1) is connected with the source electrode that the 2nd PMOS manages (T2), the source electrode of the one PMOS pipe (T1) is connected with linear voltage regulator, between the drain electrode of the one PMOS pipe (T1) and source electrode, by the second electric capacity (C2), be connected, the drain electrode of the 2nd PMOS pipe (T2) is connected with the drain electrode that a NMOS manages (T3), the source electrode of the one NMOS pipe (T3) is connected with the drain electrode that the 2nd NMOS manages (T4), between the source electrode of the 2nd NMOS pipe (T4) and drain electrode, by the first electric capacity (C1), be connected, the 2nd NMOS manages the source ground of (T4);

The input end of described polarity-inverting amplifier (U1) is connected with the grid of the 2nd PMOS pipe (T2), the grid of a NMOS pipe (T3) respectively, and the output terminal of polarity-inverting amplifier (U1) is connected with the grid of a PMOS pipe (T1), the grid of the 2nd NMOS pipe (T4) respectively.

2. low pressure difference linear voltage regulator according to claim 1, it is characterized in that, described linear voltage regulator comprises input port, output port, operational amplifier, the 3rd PMOS pipe (T5), the first resistance (R1), the second resistance (R2), the 3rd electric capacity (C3) and constant current source;

The reverse input end of described operational amplifier is connected with input port, the output terminal of operational amplifier is connected with the grid that the 3rd PMOS manages (T5), the source electrode of the 3rd PMOS pipe (T5) is connected with the source electrode that a PMOS manages (T1), the drain electrode of the 3rd PMOS pipe (T5) respectively with the in-phase input end of operational amplifier, one end of the first resistance (R1), one end of the second resistance (R2), the input end of constant current source, and output port is connected, the other end ground connection of the first resistance (R1), the other end of the second resistance (R2) and the 3rd electric capacity (C3) are connected in series rear ground connection, the output head grounding of constant current source.

3. low pressure difference linear voltage regulator according to claim 1, it is characterized in that, while being switched to zero when the voltage of the voltage of described the first electric capacity (C1) one end and the second electric capacity (C2) one end is switched to high level from zero or from high level, the voltage of the voltage of the first electric capacity (C1) other end and the second electric capacity (C2) other end can dynamically be drawn high or be dragged down, and causes the output current of the 3rd P M O S pipe (T5) to make corresponding response.