SU1744788A1 - Driver - Google Patents

Abstract

The invention relates to a pulse technique as well as to a radio measuring technique and can be used in automated measuring systems as a source of stimulating effects and adjustable pulse signals. The aim of the invention is to reduce power consumption while maintaining speed. The driver contains stages 1 and 2 of control of the duration of the front and fall of the output signal, the first and second circuits 3 and 4 of the control signal voltage level offset, the first and second circuits 5 and 6 of the displacement of the voltage level of the control signal for the third state, formation stages 7 and 8 of the front and edge of the output signal, high and low disconnection stages 9 and 10, bias and deactivation circuit 11, high and low threshold devices 12 and 13, high and low threshold devices 14 and 15, Secondly, the output stages 16 and 17. The first and second feedback devices 18 and 19, the first and second disconnect devices 20 and 21. The introduction of the first and second stages 22, 23 allows for a reduction in the total power as well as the magnitudes of the charging and discharging currents of the I and I nodes in the modes of disconnecting the third state and turning on the third state do not change, the high speed is preserved. 2 Il. -N XI with oo Fp1 ///

Description

The invention relates to a pulse technique as well as to a radio measuring technique and can be used in automated measuring systems (AIS) of dynamic and functional monitoring of integrated circuit (IC) parameters of various classes as a source of stimulating effects for the device under test.

The aim of the invention is to reduce power while maintaining high speed.

FIG. 1 shows a driver flowchart; in fig. 2 - basic electrical driver circuit.

The driver (Fig. 1) contains a cascade 1 for controlling the duration of the front of the output signal and a cascade 2 for controlling the duration of the decay of the output signal, respectively connected to the bus Ef of controlling the duration of the front of the output signal and to the bus. It controls the duration of the decay of the output signal, the first 3 and second 4 offsets the voltage levels of the control signals, the first and second inputs of which are connected respectively to the buses of the direct Uy and inverse Uy digital control signals, the first 5 and second b of the voltage level offset circuit control signal state of the third, first and second inputs of which are respectively connected to buses Ua forward and inverse digital control signals Us third state of. To the non-inverting inputs of the output stage formation stage 7 and the output signal falling stage formation stage 8, respectively, the output of the first 3 voltage level offset circuits, which are non-inverting relative to the first input, are connected to the output of the second 4 voltage control voltage offset circuits, which inverts the cascades, relative to the first input. forming the front 7 and decay 8 of the output, the signal is connected, respectively, the output of the first 3 inverting relative to the first input and non-inverting With respect to the first input, the output of the second 4 control voltage level offset circuits, and the output of the output signal front edge and the output control of the output signal stage cascade 8 are connected to the output edge output stage and cascade 2 control input, respectively, to the output input of the output stage cascade 7. control the duration of the decay of the output signal. To the first and second inputs, respectively, of the high level and

the low level switch-off stage 10 is connected to the inverting and non-inverting respectively to the first input outputs of the first 5 and

the second 6 schemes for shifting the voltage levels of the control signals of the third state. To the input of the bias and disconnection circuit 11, the outputs of the cascade 7 of forming the front of the output signal are connected and

0 of the high-level threshold device 12, and the output of the bias circuit and disconnection 11 are connected to the outputs of the cascade 8 of the output signal decay and the low-level threshold device 13, whose input and input of the high-level threshold device 14 are connected to a low voltage bus, and the input of the threshold device 12 is high and the threshold device 15 off low level connected to the bus EV high

0 voltage level The output of the high-level cutoff device 14 and the first input of the first output stage 16 are connected to the input, and the output of the low-level switch-off device 15 and

5, the first input of the second output stage 17 is to the output of the bias and disconnection circuit 11. The outputs of the first 16 and second 17 output stages are connected respectively to the inputs of the first 18 and second 19 devices

0 feedback, the outputs of which are connected respectively to the inputs of the first 20 and second 21 disconnecting devices, the outputs of which are connected to the output bus. The first inputs of the first 22 and second 23 cascades

5 disconnections are connected respectively to the outputs of the output control stage 1 and the output stage decay stage 2, the output stage decay, the outputs respectively to the output and the input of the bias circuit 11 and disconnection, and the second inputs correspond respectively to the disconnecting outputs 9 of the cascade 9 high level and low-level cascade 10, non-inverting with respect to the first inputs, the outputs of which are connected respectively to the third inputs 3 and the second 4 levels shifting schemes voltage control signals. The second inputs of the first 16

0 and the second 17 output stages are connected respectively to the bus + Ei of the positive voltage source of the output stage and to the bus -Ea negative voltage source of the output stage.

5 The first disconnection stage 22, with diode 24, a resistor 25 and a pn-n transistor 26, is shown (FIG. 2), the collector of which is the output of the cascade and the base is the second input of the cascade, while the cathode of the diode 24 is connected to

the emitter of the transistor 26. its anode is the first input of the cascade, and the base of the transistor 26 through a resistor 25 is connected to the second bus of a positive voltage source.

The second switch-off stage 23 contains (FIG. 2) a diode 27, a resistor 28 and a np-n type transistor 29, whose collector is the stage output and the base is the second stage input, while the anode of the diode 27 is connected to the emitter of the transistor 29, its cathode is the first input of the cascade, and the base of the transistor 29 through the resistor 28 is connected to the second bus of the negative voltage source.

The first bias voltage control circuit 3 contains (Fig. 2) the first 30 and second 31 transistors of the np-n type, the base of the first transistor 30 being the second input of the circuit, the base of the second transistor 31 being the first input of the circuit, the combined emitters of the first 30 and the second 31 transistors are the third input of the circuit, while the collector of the first transistor 30 is the inverting output of the circuit, and the collector of the second transistor 31 is the non-inverting output of the circuit.

The second 4 voltage control voltage offset circuit comprises (FIG. 2) first 32 and second 33 pn-p transistors of type, with the base of the first transistor 32 being the second input of the circuit, the base of the second transistor 33 being the first input of the circuit, combined nepeqro emitters 32 and the second 33 transistors are the third input of the circuit, while the collector of the first transistor 32 is the non-inverting output of the circuit, and the collector of the second transistor 33 is the inverting output of the circuit.

The driver works as follows.

To switch the output voltage levels and to enable and disable the third state mode, the driver requires differential digital signals matched with the ECL logic levels of the control input (Uy and Oy) and the input of the third state control (Oz and Da). The differential control signal is supplied to the inputs of the first 3 and second 4 control voltage level offset circuits, which provide a differential switching current, respectively, to the output edge shaping stage 7 and the output signal dropping stage 8, and the third state control signal is fed to the inputs the first 5 and second 6, the voltage level offset circuits

control of the third state, which produce a differential switched current, respectively, on the high level switching stage 9 and on the low level stage 10 5. At the same time, at a high voltage level at the first inputs of the 3-6 displacement circuits, the currents flowing through their inverting outputs are low.

0 When the voltage level of the direct digital control signal is low, the third state U3 flows through the resistors 36 and 39, respectively, of the first 5 and second b levels of the offset circuit

5, the voltages of the third state control signals are switched to transistors 35 and 38, respectively, and the currents flowing through transistors 34 and 37, respectively, are zero. In cascade 9 off

0 high level and in cascade 10 off low level this leads to an increase in voltage drops on resistors, respectively, 61 and 66, and a decrease in voltage drops on resistors, respectively

5 62 and 67, which, in turn, leads to the switching of the currents flowing through the resistors 60 and 65, respectively, into the transistors, respectively, 58 and 63, and the currents flowing through the transistors, respectively, 59 and 64, are equal to zero. Thus, the high-level cut-off stage 9 and the low-level turn-off stage 10 activate the transistors 30, 31 and 32, respectively, of the first 3 and second 4, respectively.

5 control voltage level offset circuits, while in the tripping stages, respectively, the first 22 and second 23 voltage drops on the resistors, respectively, 25 and 28 are zero, and

0 emitter transitions of transistors, respectively, 26 and 29 and diodes, respectively, 24 and 27 are shifted in the opposite direction. Thus, the first 22 and second 23 deactivation cascades are inactive and they have no effect on the processes occurring at. nodes, respectively, II and I drivers.

In the mode of operation of the driver with the maximum speed of the voltage on the front-side control bus

0 of the output signal Ef and on the control bus of the duration of the output signal decay It is equal to zero and the output currents of the cascade 1 control the duration of the front of the output signal and the cascade 2 control the duration of the decay of the output signal are zero. At a low voltage level on the direct digital control bus Uy, the currents flowing through the transistors, respectively, 58 and 63, are switched to the transistors, respectively, 30 and 33 of the first 3 and

The second 4 control voltage level offset circuits, and the currents flowing through the transistors 31 and 32, respectively, are equal to zero. In the cascade 7 of the front of the output signal and in the cascade 8 of the decay of the output signal, this leads to an increase in voltage drops on the resistors, respectively 47 , 45 and 57, 55 and reducing the voltage drops across the resistors, respectively, 48, 46 and 56, 54. As a result, the currents flowing through the resistors, respectively, 44 and 53 switch through the diodes, respectively, 42 and 52, to transistors, respectively, 40 and 50. At the same time, the diodes 43 and 51, respectively, are biased in the opposite direction, and the currents of resistors, 46 and 54, respectively, flow through the transistors, 41 and 49, respectively. The currents flowing through the resistors, respectively, 44.45, 46 and 53, 54, 55, are determined by the values of their resistances , power supplies of the driver stages, respectively + VC, + VCo and -Vet - VBO, with | + Vc I 1+ Vco I and l-Ve l I -V / Bol, as well as voltage drops across the diodes, respectively 42 , 43 and 51, 52. emitter transitions of transistors, respectively, 40, 41 and 49, 50. At the same time, the current flowing through tr The anzistor 46 provides the operating mode of the bias and disconnection circuit 11 containing diodes 68-72, namely, it provides the voltage drop between the driver I and II nodes and keeps it constant, and also provides the input current bias of the first output stage 16 containing the transistor 77 The current flowing through the resistor 53 provides the discharge of the parasitic capacitance of node II, and also provides through the low resistance of the forward-shifted diodes 68-72 of the bias circuit 11 and disconnects the discharge of the parasitic capacitance of node I. As a result Yes, the parasitic capacitances of the nodes t and driver II, the voltage at these nodes decreases. The voltage reduction at node II occurs before the opening of the low-level threshold device 13 containing diode 74. As a result, most of the current flowing through. the transistor 50. switches through the diode 74 to the low voltage level En, and the node U is set to voltage UH - Udn, where UH is the voltage to the low voltage level Yon; 1) Dn - the voltage drop across the diode 74, and a smaller part of the current provides the operating mode of the bias and disconnect circuit 11 and the input bias current of the second output stage 17 containing transistor 78. Since the voltage drop between the driver I and II nodes is determined by the current flowing through the resistor 46 and not dependent on the current flowing through the transistor 50, then between the driver I and II nodes is supported

constant voltage, which provides the mode of operation of the first 16 and second 17 output stages, containing respectively transistors 77 and 78 for the voltage. The first 18 and second 19 reverse devices

0 connection, containing resistors 79 and 80, respectively, as well as first 20 and second 21 disconnect devices, containing diodes 81 and 82, respectively, provide the quiescent current of the first 16 and second transistors 17

5 output stages. Moreover, the voltage changes in the driver I and I nodes are transmitted to the output bus Uvih. Thus, a low voltage is generated on the driver output bus,

0 When the voltage level of the direct digital control signal is high, the currents flowing through the transistors 58 and 63 are switched to the transistors, respectively, 31 and 32 of the first 3 and second 4 circuits

5, the voltage levels of the control signals are shifted, and the currents flowing through the transistors, 30 and 33, respectively, are zero. In the cascade 7 of the formation of the front of the output signal and in the cascade 8 of the formation of a drop in the output signal, this leads to an increase in the voltage drops on the resistors, 48, 46 and 56, 54, respectively, and to a decrease in the voltage drops on the resistors, respectively 47. 45 and 57. 55. AT

5, the currents flowing through the resistors, respectively, 44 and 53, respectively, switch through the diodes 43 and 51, respectively, to the transistors, respectively, 41 and 49. At the same time, the diodes, respectively, 42 and 52 are biased in the opposite direction and, respectively, through the transistors, 40 and 50 and 55. Moreover, the current flowing through the resistor 55 provides the operating mode of the circuit 11

5 bias and disconnects containing diodes 68-72, namely, it provides the voltage drop between the driver I and II nodes and keeps it constant, and also provides the input bias current of the second output stage 17 containing the transistor 78. Current. Flowing through the resistor 44 provides the charge for the parasitic capacitance of node I, and also provides the low resistance of the parasitic capacitance of node II through the low resistance in the forward direction of the diodes 68-72 of the bias circuit 11 and the disconnection of the charge. As a result of the charge of parasitic capacitances of the nodes I and II, the voltage drivers at these nodes increase. An increase in voltage at node I occurs

prior to opening the threshold device 12. a high level containing diode 73. As a result, most of the current flowing through the transistor 41 is switched through the diode 73 to the high voltage bus E, and the node U of the driver sets the voltage UB + and where UB is the voltage on the high voltage bus EV; 11dv is the voltage drop across the diode 73, and a smaller part of the current provides the operating mode of the bias and disconnection circuit 11 and the input bias current of the first output stage 16 containing transistor 77. Since the voltage drop between the driver I and II nodes is determined by the current flowing through the resistor 55i and does not depend on the current flowing through the transistor 41, then a constant voltage is maintained between the driver I and II nodes, which ensures the operation of the first 16 and second 17 output stages, containing respectively transistors 77 and 78 apr. The first 18 and second 19 feedback devices, containing resistors 79 and 80, respectively, as well as the first 20 and second 21 disconnect devices, containing diodes 81 and 82, respectively, provide the quiescent current of the first 16 and second 17 output transistors. Moreover, the voltage changes in the driver I and II nodes are transmitted to the output busbar and the high level voltage is formed on the driver output bus.

The front and fall durations of the driver output signal are controlled as follows.

With non-zero voltages on the control bus for the front duration of the output signal Ef and on the control bus for the duration of the fall of the output signal. Its output currents of the output control stage 1 of the output signal and of the output stage 2 control do not equal zero. In this case, the output currents of these stages are respectively the inflowing and outflowing currents. As a result, the current switched through the diodes 42 and 43 in the stage 7 of the formation of the front of the output signal is reduced, and the current switched through the diodes 51 and 52 in the stage 8 of the formation of the drop in the output signal, which in turn leads to a decrease magnitudes of charge and discharge currents of parasitic capacitances of nodes I and II of the driver. Therefore, the voltage measurement rates at the driver I and II nodes are reduced, which means that the front and fall durations of the driver output signal are increased.

At a high voltage level on the bus of the direct digital control signal of the third state 1), the currents flowing through the resistors 36 and 39, respectively, of the first 5 and second 6 voltage level offset circuits of the control signals of the third state, are respectively switched to transistors 34 and 37 and the currents flowing through the transistors 35 and 38, respectively, are zero. In the high-level stage 9 and the low-level stage 10, this leads to an increase in the voltage drops on the resistors, respectively 52 and 67 and a decrease in the voltage drops on the resistors, respectively, 61 and 66, which in turn leads to the switching of the currents flowing respectively, through resistors 60 and 65 to transistors, respectively, 59 and 64, and the currents flowing through transistors, respectively, 58 and 63, are zero. Thus, the high-level cut-off stage 9 and the low-level turn-off stage 10 turn the transistors of the first 3 and second 4 voltage level bias circuit of the control signals, respectively 30, 31 and 32, 33, to an inactive state, which, in turn, leads to stage 7 of the formation of the front of the output signal and in stage 8 of the formation of a drop in the output signal to reduce the voltage drops on the resistors, respectively, 47,45,48, 46 and 56,54,57,55, and in the first 22 and second 23 disconnection stages increase the voltage Resistors match but 25 and 28, which, in turn, leads to a displacement in the forward direction of the emitter transitions of transistors, respectively 26 and 29, and diodes, respectively, 24 and 27. As a result, in the cascade 7 the formation of the front of the output signal and in the cascade 8 of the formation of the output decay Signal diodes, respectively, 42, 43 and 51, 52 are biased in the opposite direction and resistors flow through 40, 41 and 49, 50 resistors, respectively, 45.46 and 54, 55, and currents flowing through resistors, respectively, 44 and 53, respectively, switch through first 22 and second 23 disable cascades respectively in the I and in the I driver nodes. The currents flowing through the resistors, respectively, 44 and 53, or more than the currents flowing through the resistors, respectively, 46 and 55. The difference in the currents flowing through the resistors, respectively, 44, 55 and 53, 46, occurs respectively, the parasitic capacitance of the driver II and the parasitic capacitance node I driver. The voltage changes at these nodes occur before opening the cut-off devices, respectively, low level 15 and high level 14, containing diodes 76 and 75, respectively, and switching the charge current of the parasitic capacitance of the driver II node and the current of the parasitic capacitance of the driver node, respectively, to the high bus the voltage level of the EV and into the low voltage bus Ei. In this case, the voltage is set at the nodes I and I of the driver: Ui Un - 11 days and Un UB + 11dvp, where Ui and Un are the voltage at nodes I and II of the driver; Us, UH voltage on tires of high EV and low Yon voltage levels; Udil and idvp - voltage drops on diodes 75 and 76 respectively. As a result, the input and output of the bias and disconnection circuit 11 and the first inputs of the first 1 b and second 17 output stages are connected to reverse voltages, which leads to a reverse bias of diodes 68-72 and emitter transitions of transistors 77 and 78.

Thus, the driver output is disconnected from the output bus. those. a third state mode is provided. In this case, the first 20 and second 21 disconnect devices, containing diodes 81 and 82, respectively, protect the first 16 and second 17 output stages, namely, protect the emitter transitions of the transistors 77 and 78, respectively, that are emitted from the breakdown in the reverse direction. low-capacitance schottky diodes as the first 20 and second

The 21 shutdown devices provide low driver output capacity in the third state mode.

Introduction to the structural diagram of the first

22 and the second 23 shutdown stages can reduce power consumption or power sources.

This is primarily due to the fact that, compared with the prototype, the power consumed by the high-level cascade 9 and the low-level cascade 10 is significantly reduced. This reduction in power is achieved by changing the functioning of the cascades 9 and 10 of the proposed device as compared with the prototype.

In the proposed device, the operation of cascades 9 and 10 in the disconnected third state mode leads to the activation of transistors 30, 31 and 32, 33 of the first 3 and second 4, respectively, of the voltage level offset control signals and the transition to the inactive state of the first 22 and second, respectively

The 23 cascades are turned off, and in the on state of the third state, the transistors 30,31 and 32,33 are switched to the inactive state and the first 22 and second 23 stages of the outage are activated, respectively. These cascades, in turn, together with the first 3 and second 4, respectively, of the voltage level control circuit bias of the control signals ensure that the inactive state, respectively, of the output edge formation stage 7

0 of the signal and the cascade 8 of formation of the output signal decay and switching of the charging current of node I and the discharge current of node II, respectively, into node II and node I of the driver.

Thus, the functioning

5 of the first 22 and second 23 shutdown stages, together with the first 3 and second 4 control voltage offset circuits, ensure the use of charge and discharge currents of nodes I and II as for

0 forming and switching the output signal of the driver, and for switching on the mode of the third state. This provides a significant reduction in the power consumed by the stage 9 off high

Level 5 and cascade 10 low level trip. As a result, the total power consumed by the driver is reduced. And since in this case the magnitudes of charge and discharge currents of the I and II nodes when the driver is working and the modes

0 the disconnected third state and the activated third state do not change, then the high performance, including switching to the third state mode, is preserved.

Claims (1)

5 claims A driver containing the first and second voltage level offset circuits of the control signals of the third state, the first and second inputs of which are connected 0, respectively, to the direct and inverse digital control signals of the third state, and their inverting and non-inverting outputs relative to the first input are connected respectively 5 to the first and second inputs, respectively, of the high-level cut-off stage and the low-level cut-off stage, the first and second inputs of the first and second control voltage level bias circuits are not connected to the direct and inverse digital control buses, respectively, and they are inverting relative to the first input outputs are connected respectively to the inverting 5 input stage of the formation of the front of the output signal and to the non-inverting input of the cascade formation of the decay of the output signal, and their non-inverting outputs relative to the first input are connected respectively to the non-inverting input output front stage and to the inverting input of the output decay stage cascade, the output edge control stage and output decay stage cascade inputs are connected to the output front length control line and the output signal duration control bus, and their outputs connected respectively to the third input of the cascade of formation of the front of the output signal and to the third input of the cascade of formation of the decay you a single signal, the outputs of the output edge cascade, the high-level threshold device and the high-level threshold device are combined with the first input of the first output stage and connected to the bias-and-off circuit input, and the outputs of the output signal cascade, the low-level device threshold and the low-level cutoff device is combined with the first input of the second output stage and connected to the output of the bias and trip circuit, with the threshold inputs the high level devices and the threshold disconnect device are connected to the high voltage bus, and the inputs of the low threshold device and the switch disconnect device are connected to the low voltage bus, the outputs of the first and second disconnect devices are connected to the output bus their inputs and outputs, respectively, of the first and second output stages include, respectively, the first and second feedback devices, with the second inputs of the first and second output stages Ascadas are connected respectively to the bus of the positive voltage source of the output stage and to the bus of the negative voltage source of the output stage, characterized in that, in order to reduce power consumption while maintaining speed, the first and second disconnection stages are inserted into it, the first inputs of which are connected respectively to the output of the output control stage cascade and the output of the output control cascade for the duration of the output signal decay, the second inputs to the inverting outputs of the high level and low cutoff stages corresponding to the first input, and the outputs to the first inputs of the second and first output stages, respectively, while non-inverting relative to the first input 0 the outputs of the high-level cut-off stage and the low-level cut-off stage are respectively connected to the third inputs of the first and second signal voltage offset circuits respectively 5, wherein the first disconnect stage comprises a diode, a resistor, and a pn-p type transistor, the collector of the transistor being the output of the cascade, the base of the transistor being the second input of the cascade, and 0 anode of the diode - the first input of the cascade, while the cathode of the diode is connected to the emitter of the transistor, the base of which is connected via a resistor to the positive voltage source bus, and the second stage disconnects 5 the diode, resistor and npn-type transistor, the cascade, the base of the transistor is the second input of the cascade, and the cathode of the diode - the first input of the cascade, while the anode 0 of the diode is connected to the emitter of the transistor, the base of which, via a resistor, is connected to the negative voltage source bus, the first control voltage offset circuit contains 5, the first and second transistors are pn-type, the base of the first and second transistors being the second and first inputs of the circuit respectively, the combined emitters of the transistors being the third input 0 circuits, and the collectors of the first and second transistors — Zistorov, respectively, the inverting and non-inverting outputs of the circuit, and the second circuit for shifting the voltage levels of the control signals contains the first and 5, the second pnp type transistors, the bases of the first and second transistors being the second and first circuit inputs, respectively, the combined emitters of the transistors being the third circuit input, and 0 collectors of the first and second transistors - accordingly non-inverting and inverting circuit outputs.