RU2513489C2 - Multi-differential operational amplifier - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: invention relates to radio engineering and communication and can be used as a broadband signal amplifier, in analogue interfaces, analogue-to-digital converters, RC filters, instrumentation amplifiers etc. The multi-differential operational amplifier includes an input differential voltage-to-current converter, anti-phase current outputs, two-terminal loads, power supply buses, current outputs of the device, input transistors, an input transistor emitter, power sources, reference current sources, scaling resistors, the reference current sources are in form of controlled reference current sources with corresponding control inputs which are connected to the output of the stage for selecting the output in-phase voltage of the input differential voltage-to-current converter, wherein inputs of the stage for selecting the output in-phase voltage of the input differential voltage-to-current converter are connected to corresponding anti-phase current outputs of the input differential voltage-to-current converter.

EFFECT: high coefficient of attenuation of input in-phase signals of a multi-differential operational amplifier, wider operating frequency range, low temperature drift of the zero offset emf, high input cut-off voltage.

4 cl, 13 dwg

Description

The invention relates to the field of radio engineering and communication and can be used as a device for amplifying broadband signals, in the structure of analog interfaces, analog-to-digital converters, RC filters, instrumental amplifiers, etc.

Known circuits of the so-called multidifferential operational amplifiers (MOU), having several inputs and a common output subcircuit - buffer cascade [1-8]. Due to the low energy consumption, the MOCs became the basis of many new generation microelectronic devices [1-8].

The closest prototype of the claimed device (figure 1) is a multidifferential operational amplifier described in US patent No. 4835488, fig.3. It contains the first 1 input differential voltage-to-current converter, the first 2 and second 3 antiphase current outputs of which are connected to the corresponding first 4 and second 5 antiphase current outputs of the second 6 input differential voltage-current converter, the first 7 two-pole load connected between the first 8 bus of the power source and the first 2 current output of the first 1 input differential voltage-current converter connected to the first 9 output of the device, the second 10 two-terminal load ki, the second 11 output of the device, the first 1 input differential voltage-current converter including the first 12 and second 13 input transistors, the bases of which are connected to the first group 14, 15 of the corresponding antiphase inputs 14, 15 of the device, the emitter of the first 12 input transistor is connected with the second 16 bus of the power source through the first 17 source of reference current, the emitter of the second 13 input transistor is connected with the second 16 bus of the power source through the second 18 source of reference current, between the emitters of the first 12 and second 13 input t the first 19 scaling resistor is included in the resistors, the second 6 input voltage-current differential converter including a second 10 load two-pole connected between the first 8 bus of the power supply and the second 3 current output of the first 1 input differential voltage-current converter connected to the second 5 by the current output of the second 6 input differential voltage-current converter and the second 11 output of the device, and the second 6 input differential voltage-current converter includes there is a third 20 and a fourth 21 input transistors, the bases of which are connected to the second group (22, 23) of the antiphase inputs 22, 23 of the device, the emitter of the third 20 input transistor is connected to the second 16 bus of the power source through the third 24 reference current source, the emitter of the fourth 21 input the transistor is connected to the second 16 bus of the power source through the fourth 25 source of the reference current, between the emitters of the third 20 and fourth 21 input transistors included a second 26 scaling resistor.

A significant drawback of the known DE of FIG. 1 is that it has a relatively low attenuation of the input common-mode signals, which negatively affects the accuracy parameters of the analog interfaces based on it.

The main objective of the invention is to increase the attenuation coefficient of the input common-mode signals of the MOU, as well as expanding the range of operating frequencies, reducing the temperature drift of the EMF of a zero bias, and increasing the input boundary stresses.

The problem is achieved in that in the multidifferential operational amplifier of figure 1, containing the first 1 input differential voltage-current converter, the first 2 and second 3 antiphase current outputs of which are connected to the corresponding first 4 and second 5 antiphase current outputs of the second 6 input differential voltage-current converter, the first 7 two-pole load connected between the first 8 bus of the power source and the first 2 current output of the first 1 differential input converter voltage-current "connected to the first 9 output of the device, the second 10 bipolar load, the second 11 output of the device, and the first 1 input differential voltage-current Converter includes the first 12 and second 13 input transistors, the bases of which are connected to the first group 14, 15 of the corresponding antiphase inputs 14, 15 of the device, the emitter of the first 12 input transistor is connected to the second 16 bus of the power source through the first 17 source of reference current, the emitter of the second 13 input transistor is connected to the second 16 bus of the source and power is supplied through the second 18 source of the reference current, between the emitters of the first 12 and second 13 input transistors, the first 19 scaling resistor is turned on, and the second 6 input differential voltage-current converter includes a second 10 two-pole load connected between the first 8 bus of the power source and the second 3 current output of the first 1 input differential voltage-current converter connected to the second 5 current output of the second 6 input differential voltage-current converter and second 11 output ohms of the device, the second 6 input differential voltage-current converter including the third 20 and fourth 21 input transistors, the bases of which are connected to the second group (22, 23) of the phase inputs 22, 23 of the device, the emitter of the third 20 input transistor is connected to the second 16 the power supply bus through the third 24th reference current source, the emitter of the fourth 21 input transistor is connected to the second 16th power supply bus through the fourth 25th reference current source, between the emitters of the third 20 and the fourth 21 input transistors a second 26 scaling resistor is provided, new elements and connections are provided, the first 17 and second 18 reference current sources are made in the form of controlled reference current sources with corresponding control inputs 27 and 28, which are connected to the output of the output common-mode voltage isolation stage 29 of the first 1 input differential converter voltage-current ", and the inputs of the cascade 29 for selecting the output common-mode voltage of the first 1 input differential voltage-current converter are connected to the corresponding the first 2 and second 3 antiphase current outputs of the first 1 "voltage-current" input differential converter.

The amplifier circuit of the prototype is presented in figure 1. Figure 2 shows the claimed MOA in accordance with claims 1 to 4 of the claims.

Figure 3 presents a schematic diagram of the inventive device on CMOS transistors.

The circuit studied by the authors of the MOU (figure 2) in the computer simulation environment Cadance Virtuoso on models of SiGe transistors is presented in figure 4.

Figure 5 shows the frequency dependence of the transfer coefficient of the common-mode voltage of the MOA of figure 4 at a unit differential gain.

Figure 6 shows graphs for determining the boundary voltage of the input common-mode signal of the MOU of figure 4, within which a high level of attenuation of the input common-mode voltage is provided.

In Fig.7 presents the amplitude-frequency characteristic of the MOA (Fig.4), and Fig.8 - its phase-frequency characteristic.

Figure 9 shows the amplitude-frequency characteristic of the MOA of figure 4 in the non-inverting voltage follower mode.

Figure 10 shows graphs for determining the maximum slew rate of the output voltage of the MOA of figure 4, and figure 11 is its amplitude characteristic.

In Fig.12 shows the temperature dependence of the EMF bias MOW (Fig.4).

The multi-differential operational amplifier of FIG. 2 comprises a first 1 input differential voltage-current converter, the first 2 and second 3 antiphase current outputs of which are connected to the corresponding first 4 and second 5 antiphase current outputs of the second 6 voltage-current input differential converter, the first 7 two-pole load connected between the first 8 bus power source and the first 2 current output of the first 1 input differential voltage-current Converter connected to the first 9 the output of the device, the second 10 bipolar load, the second 11 output of the device, and the first 1 input differential voltage-current converter includes the first 12 and second 13 input transistors, the bases of which are connected to the first group 14, 15 of the corresponding antiphase inputs 14, 15 of the device , the emitter of the first 12 input transistor is connected to the second 16 bus of the power source through the first 17 reference current source, the emitter of the second 13 input transistor is connected to the second 16 bus of the power source through the second 18 source of reference a, between the emitters of the first 12 and second 13 input transistors, the first 19 scaling resistor is turned on, and the second 6 input differential voltage-current converter includes a second 10 two-terminal load connected between the first 8 bus of the power source and the second 3 current output of the first 1 differential input a voltage-current converter connected to a second 5 current output of the second 6 input differential voltage-current converter and a second 11 output of the device, the second 6 input differential The voltage-current converter includes the third 20 and fourth 21 input transistors, the bases of which are connected to the second group (22, 23) of the device out-of-phase inputs 22, 23, the emitter of the third 20 input transistor is connected to the second 16 bus of the power source through the third 24 source reference current, the emitter of the fourth 21 input transistor is connected to the second 16 bus power supply through the fourth 25 source of the reference current, between the emitters of the third 20 and fourth 21 input transistors included a second 26 scaling resistor. To achieve this goal, the first 17 and second 18 sources of the reference current are made in the form of controlled sources of the reference current with the corresponding control inputs 27 and 28, which are connected to the output of the cascade 29 of the output output common-mode voltage of the first 1 input differential voltage-current converter, and the inputs a cascade 29 for isolating the output common-mode voltage of the first 1 input differential voltage-current converter is connected to the corresponding first 2 and second 3 antiphase current the outputs of the first 1 input differential voltage-current converter.

In Fig.2, in accordance with claim 2, the third 24 and fourth 25 sources of the reference current of the second 6 input differential voltage-current converter are made in the form of controlled sources of the reference current with the corresponding control inputs 30 and 31, which are connected to the output of the cascade 29 selection of the output common-mode voltage of the first 1 input differential voltage-current Converter.

In addition, in Fig. 2, in accordance with claim 3, as the first 12, second 13, third 20, and fourth 21 input transistors, composite transistors are used in the form of field effect transistors, the sources of which correspond to emitters, drains to collectors, and gates to bases of bipolar transistors.

In figure 2, in accordance with paragraph 4 of the claims, the outputs 11 and 9 of the device are also connected to the inputs of an additional differential buffer stage 32.

Consider the operation of a multidifferential operational amplifier (MOU) of Fig.2.

Input signals containing in-phase and differential components are supplied to the base of the first 12 input transistor and the base of the second 13 input transistor. In this case, increments of the currents i ₁₂ , i ₁₃ occur, and due to the use of the first 19 scaling resistor connected between the outputs of the first 17 and second 18 sources of the reference current, the common-mode subtraction and summation of the differential components of the increments of the currents i ₁₂ , i ₁₃ occur, resulting in on the first 7 and second 10 two-terminal loads, voltage drops of the summed differential and residual current increments i ₁₂ , i ₁₃ remaining after partial subtraction of the common-mode components occur _.

The presence of a cascade 29 for isolating the output common-mode voltage of the first 1 input differential voltage-current converter allows you to create two negative feedback loops:

1. The first circuit. “The first 2 output of the first 1 input differential voltage-to-current converter” - the output of the cascade 29 for isolating the output common-mode voltage of the first 1 input differential converter “voltage-current” - the control input 27 of the first 17 reference current source - the output of the first 17 reference current source - emitter the first 12 input transistor is the collector of the first 12 input transistor ";

2. The second circuit. "The second 3 output of the first 1 input differential voltage-current converter - output of the cascade 29 of the output common-mode voltage output of the first 1 input differential voltage-current converter - control input 28 of the second 18 reference current source - output of the second 18 reference current source - emitter the second 13 input transistor is the collector of the second 13 input transistor. "

These negative feedback loops provide additional suppression of the common-mode components due to their summation on the cascade 29 for isolating the output common-mode voltage of the first 1 input differential voltage-current converter.

At the same time, these circuits do not affect the differential (antiphase) components of the voltage drops at the first 7 and second 10 two-terminal loads due to a zero result when they are summed by the cascade 29 for isolating the output common-mode voltage of the first 1 input differential voltage-current converter.

Similarly to the described principle of operation of the first 1 input differential voltage-current converter with the first 7 and second 10 two-terminal loads and a cascade 29 for isolating the output common-mode voltage of the first 1 input differential voltage-current converter, the second 6 input differential voltage-current converter operates .

After that, there is an additional amplification of the differential and attenuation of the common-mode components of the voltages at the first 7 and second 10 two-terminal loads using an additional differential buffer stage 32, the output of which is the output of the MOA.

The analysis of the scheme allows you to determine the transmission coefficients for each of the channels of the MOU

$$K_{\mathrm{one}}^{+}\left(j\omega \right)=\frac{u_{\mathrm{AT}sx.\sum }\left(j\omega \right)}{u_{\mathrm{fifteen}}\left(j\omega \right)}=-K_{\mathrm{one}}^{-}=-\frac{u_{\mathrm{AT}sx.\sum }\left(j\omega \right)}{u_{\mathrm{fourteen}}\left(j\omega \right)}=\left(S_{\mathrm{uh}12}\left(j\omega \right)Z_{n7}+S_{\mathrm{uh}13}\left(j\omega \right)Z_{n10}\right)K\left(j\omega \right),\left(\mathrm{one}\right)$$

$$K_2^{+}\left(j\omega \right)=\frac{u_{\mathrm{AT}sx.\sum }\left(j\omega \right)}{u_{23}\left(j\omega \right)}=-K_2^{-}=-\frac{u_{\mathrm{AT}sx.\sum }\left(j\omega \right)}{u_{22}\left(j\omega \right)}=\left(S_{\mathrm{uh}\mathrm{twenty}}\left(j\omega \right)Z_{n7}^{}+S_{\mathrm{uh}21}\left(j\omega \right)Z_{n10}\right)K\left(j\omega \right).\left(2\right)$$

Here S _ei (jω) is the equivalent slope of the i-th transistor

$$S_{\mathrm{uh}12}\left(j\omega \right)=\frac{S_{12}\left(j\omega \right)}{\mathrm{one}+S_{12}\left(j\omega \right)/S_{13}\left(j\omega \right)+S_{12}\left(j\omega \right){\mathrm{<figure-callout\; id="19"\; label="R"\; filenames="00000021.png"\; state="\{\{state\}\}">R</figure-callout>}}_{19}}\approx \frac{\mathrm{one}}{{\mathrm{<figure-callout\; id="19"\; label="R"\; filenames="00000021.png"\; state="\{\{state\}\}">R</figure-callout>}}_{19}},\left(3\right)$$

$$S_{\mathrm{uh}13}\left(j\omega \right)=\frac{S_{13}\left(j\omega \right)}{\mathrm{one}+S_{13}\left(j\omega \right)/S_{12}\left(j\omega \right)+S_{13}\left(j\omega \right){\mathrm{<figure-callout\; id="19"\; label="R"\; filenames="00000021.png"\; state="\{\{state\}\}">R</figure-callout>}}_{19}}\approx \frac{\mathrm{one}}{{\mathrm{<figure-callout\; id="19"\; label="R"\; filenames="00000021.png"\; state="\{\{state\}\}">R</figure-callout>}}_{19}},\left(\mathrm{four}\right)$$

$$S_{\mathrm{uh}\mathrm{twenty}}\left(j\omega \right)=\frac{S_{\mathrm{twenty}}\left(j\omega \right)}{\mathrm{one}+S_{\mathrm{twenty}}\left(j\omega \right)/S_{21}\left(j\omega \right)+S_{\mathrm{twenty}}\left(j\omega \right){\mathrm{<figure-callout\; id="26"\; label="R"\; filenames="00000021.png"\; state="\{\{state\}\}">R</figure-callout>}}_{26}}\approx \frac{\mathrm{one}}{{\mathrm{<figure-callout\; id="26"\; label="R"\; filenames="00000021.png"\; state="\{\{state\}\}">R</figure-callout>}}_{26}},\left(5\right)$$

$$S_{\mathrm{uh}21}\left(j\omega \right)=\frac{S_{21}\left(j\omega \right)}{\mathrm{one}+S_{21}\left(j\omega \right)/S_{\mathrm{twenty}}\left(j\omega \right)+S_{21}\left(j\omega \right){\mathrm{<figure-callout\; id="26"\; label="R"\; filenames="00000021.png"\; state="\{\{state\}\}">R</figure-callout>}}_{26}}\approx \frac{\mathrm{one}}{{\mathrm{<figure-callout\; id="26"\; label="R"\; filenames="00000021.png"\; state="\{\{state\}\}">R</figure-callout>}}_{26}}.\left(6\right)$$

where S _i is the slope of the i-th transistor, R _j is the resistance of the j-th scaling resistor of the circuit, K is the differential gain of the additional differential buffer stage 32.

The attenuation coefficients of the input common-mode voltage of the first 1 and second 6 input differential voltage-current converters are respectively determined by the expressions

$$K_{\mathrm{about}\mathrm{from}\mathrm{from}n\mathrm{one}}={\left(\frac{\mathrm{one}}{\mathrm{one}+\frac{S_{13}{R}_{i17}}{\mathrm{one}+R_{i17}\left({\mathrm{<figure-callout\; id="17"\; label="S"\; filenames="00000021.png"\; state="\{\{state\}\}">S</figure-callout>}}_{17}+S_{24}\right)K_c}}-\frac{\mathrm{one}}{\mathrm{one}+\frac{S_{12}{R}_{i\mathrm{eighteen}}}{\mathrm{one}+R_{i\mathrm{eighteen}}\left(S_{\mathrm{eighteen}}+S_{25}\right)K_{\mathrm{from}}}}\right)}^{-\mathrm{one}},\left(7\right)$$

$$K_{\mathrm{about}\mathrm{from}\mathrm{from}\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="00000021.png,00000025.png"\; state="\{\{state\}\}">n</figure-callout>}2}={\left(\frac{\mathrm{one}}{\mathrm{one}+\frac{S_{21}{R}_{i24}}{\mathrm{one}+R_{i24}\left({\mathrm{<figure-callout\; id="24"\; label="S"\; filenames="00000021.png"\; state="\{\{state\}\}">S</figure-callout>}}_{24}+S_{17}\right)K_{\mathrm{from}}}}-\frac{\mathrm{one}}{\mathrm{one}+\frac{S_{\mathrm{twenty}}{R}_{i25}}{\mathrm{one}+R_{i25}\left({\mathrm{<figure-callout\; id="25"\; label="S"\; filenames="00000021.png,00000029.png"\; state="\{\{state\}\}">S</figure-callout>}}_{25}+S_{\mathrm{eighteen}}\right)K_{\mathrm{from}}}}\right)}^{-\mathrm{one}},\left(8\right)$$

where R _ij is the output differential resistance of the j-th transistor or the reference current source (17, 18, 24, 25), K _c is the voltage gain of the cascade 29 for isolating the output common-mode voltage of the first 1 input differential voltage-current converter.

R_i17(S₁₇+S₂₄)K_C>>1, R_i18(S₁₈+S₂₅)K_c>>1 и R_i24(S₂₄+S₁₇)K_C>>1, R_i25(S₂₅+S₁₈)K_C>>1,то можно найти, что: If $$$$

R _i17 (S ₁₇ + S ₂₄ ) K _C >> 1, R _i18 (S ₁₈ + S ₂₅ ) K _c >> 1 and R _i24 (S ₂₄ + S ₁₇ ) K _C >> 1, R _i25 (S ₂₅ + S ₁₈ ) K _C >> 1, then we can find that:

$$K_{\mathrm{about}\mathrm{from}\mathrm{from}n\mathrm{one}}={\left(\frac{\mathrm{one}}{\mathrm{one}+\frac{S_{13}}{\left({\mathrm{<figure-callout\; id="17"\; label="S"\; filenames="00000021.png"\; state="\{\{state\}\}">S</figure-callout>}}_{17}+S_{24}\right)K_C}}-\frac{\mathrm{one}}{\mathrm{one}+\frac{S_{12}}{\left(S_{\mathrm{eighteen}}+S_{25}\right)K_C}}\right)}^{-\mathrm{one}}.\left(9\right)$$

$$K_{\mathrm{about}\mathrm{from}\mathrm{from}\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="00000021.png,00000025.png"\; state="\{\{state\}\}">n</figure-callout>}2}={\left(\frac{\mathrm{one}}{\mathrm{one}+\frac{S_{21}}{\left({\mathrm{<figure-callout\; id="24"\; label="S"\; filenames="00000021.png"\; state="\{\{state\}\}">S</figure-callout>}}_{24}+S_{17}\right)K_C}}-\frac{\mathrm{one}}{\mathrm{one}+\frac{S_{\mathrm{twenty}}}{\left({\mathrm{<figure-callout\; id="25"\; label="S"\; filenames="00000021.png,00000029.png"\; state="\{\{state\}\}">S</figure-callout>}}_{25}+S_{\mathrm{eighteen}}\right)K_C}}\right)}^{-\mathrm{one}}.\left(10\right)$$

Thus, in the MOU of _figure 2, the coefficients K _OCHH1 , K _OCHCH2

they are minimized by the depth of feedback (K _C ) introduced into the circuit without changing the differential transmission coefficients of the channels (1) and (2). A feature of this scheme is a strict correlation of the gain of individual channels of the conversion of the input differential signal

$$\frac{K_{\mathrm{one}}^{+}}{{\mathrm{<figure-callout\; id="2"\; label="K"\; filenames="00000021.png,00000025.png"\; state="\{\{state\}\}">K</figure-callout>}}_2^{+}}=\frac{K_{\mathrm{one}}^{-}}{K_2^{-}}=\frac{R_{26}}{{\mathrm{<figure-callout\; id="19"\; label="R"\; filenames="00000021.png"\; state="\{\{state\}\}">R</figure-callout>}}_{19}}.\left(\mathrm{eleven}\right)$$

Therefore, the use of this Mou in feedback devices

provides through R ₁₉ and R _{26 the} necessary correlation and coordination of local transfer functions of complex electrical circuits.

As can be seen from (1), (2), an increase in Z _H7 , Z _H10 and the symmetry of the channels makes it possible to reduce the influence of the difference in the boundary stresses of the active elements of the circuit. In particular, the zero drift of the amplifier in the open state of the MOA is determined by the expression

$$U_{dR}=U_{dR\mathrm{one}}K,\left(12\right)$$

where U _dr1 is the zero drift of the input two-channel differential stage of the MOU, K is the differential gain of the additional differential buffer stage 32.

In addition, the boundary voltages of the input circuits of the MOU, within which their linear range of operation is provided, increase due to the use of these scaling resistors (R ₁₉ , R ₂₆ ). This leads to an increase in the slew rate of the output voltage of the MOU, and also stabilizes the operating modes of the input transistors 12, 13, 20, and 21. Indeed, the boundary voltages of the first 1 and second 6 input differential voltage-current converters are respectively determined by the following expressions

$$U_{gR\mathrm{one}}\approx U_{gR.12}^{*}+U_{gR.13}^{*}+R_{19}{I}_0,\left(13\right)$$

$${\mathrm{<figure-callout\; id="6"\; label="U\; g\; R"\; filenames="00000021.png"\; state="\{\{state\}\}">U\; </figure-callout>}}_{gR}\approx U_{gR\mathrm{.twenty}}^{*}+U_{gR.21}^{*}+R_{26}{I}_0^{},\left(\mathrm{fourteen}\right)$$

where I ₀ = I ₁₇ = I ₁₈ = I ₂₄ = I ₂₅ are the static currents of the reference current sources 17, 18, 24, 25.

- граничное входное напряжение i-го транзистора $$\left(U_{гр.i}^{*}\approx 25мВ\right)$$

. $$U_{gR.i}^{*}$$

- boundary input voltage of the i-th transistor $$\left(U_{gR.i}^{*}\approx 25m\mathrm{AT}\right)$$

.

An increase in the boundary stresses (13) and (14) due to the resistors R ₁₉ and R ₂₆ reduces the influence of the manufacturing error of the input converters of transistors 12, 13; 20, 21 for currents of equivalent loads and, therefore, zero drift. As can be seen from the formulas

$$i_{\mathrm{12,}\left(13\right)}\left(\Delta U^{*}\right)=\frac{{\mathrm{<figure-callout\; id="12"\; label="S"\; filenames="00000021.png,00000022.png"\; state="\{\{state\}\}">S</figure-callout>}}_{\mathrm{12,}\left(13\right)}\Delta U^{*}}{\mathrm{one}+{\mathrm{<figure-callout\; id="12"\; label="S"\; filenames="00000021.png,00000022.png"\; state="\{\{state\}\}">S</figure-callout>}}_{\mathrm{12,}\left(13\right)}{\mathrm{<figure-callout\; id="19"\; label="R"\; filenames="00000021.png"\; state="\{\{state\}\}">R</figure-callout>}}_{19}+{\mathrm{<figure-callout\; id="12"\; label="S"\; filenames="00000021.png,00000022.png"\; state="\{\{state\}\}">S</figure-callout>}}_{\mathrm{12,}\left(13\right)}/{\mathrm{<figure-callout\; id="13"\; label="S"\; filenames="00000021.png"\; state="\{\{state\}\}">S</figure-callout>}}_{\mathrm{13,}\left(12\right)}}\left(\mathrm{fifteen}\right)$$

$$i_{\mathrm{twenty,}\left(21\right)}^{}\left(\Delta U^{*}\right)=\frac{S_{\mathrm{twenty,}\left(21\right)}\Delta U^{*}}{\mathrm{one}+S_{\mathrm{twenty,}\left(21\right)}{\mathrm{<figure-callout\; id="19"\; label="R"\; filenames="00000021.png"\; state="\{\{state\}\}">R</figure-callout>}}_{19}+S_{\mathrm{twenty,}\left(21\right)}/{\mathrm{<figure-callout\; id="21"\; label="S"\; filenames="00000021.png"\; state="\{\{state\}\}">S</figure-callout>}}_{\mathrm{21,}\left(\mathrm{twenty}\right)}},\left(16\right)$$

where ΔU ^∗ is the technological difference of the boundary stresses of the input converters, this leads to increased stability of the operating modes of the active elements of the input circuits of the MOU.

The results of computer simulation of the MOU presented in the graphs of Figures 5-12? confirm that the inventive device has higher values of the attenuation coefficient of the input common-mode signals and is characterized by improved values of other parameters.

The proposed MOU can be used in the structure of broadband interfaces, sensor and measurement systems.

BIBLIOGRAPHIC LIST

1. Patent US 4835488, fig. 3.

2. Patent application US 2008/0064359, fig. 4.

3. Patent US 7205799, fig. 4.

4. Patent application WO 2007/022705.

5. Patent US 7271647.

6. The patent of Germany 2146418.

7. Patent application US 2003/0084377.

8. Patent US 5045804, fig. 2.

Claims (4)

1. A multidifferential operational amplifier containing the first (1) input differential voltage-current converter, the first (2) and second (3) antiphase current outputs of which are connected to the corresponding first (4) and second (5) antiphase current outputs of the second ( 6) the input voltage-current differential converter, the first (7) two-terminal load connected between the first (8) bus of the power source and the first (2) current output of the first (1) input differential voltage-current converter, connected m with the first (9) output of the device, the second (10) two-terminal load, the second (11) output of the device, the first (1) input differential voltage-current converter including the first (12) and second (13) input transistors, bases which are connected to the first group (14), (15) of the corresponding antiphase inputs (14), (15) of the device, the emitter of the first (12) input transistor is connected to the second (16) bus of the power supply through the first (17) reference current source, emitter the second (13) input transistor is connected to the second (16) bus of the power supply via the WTO swarm (18) reference current source, between the emitters of the first (12) and second (13) input transistors, the first (19) scaling resistor is turned on, and the second (6) input differential voltage-current converter includes a second (10) two-pole load, connected between the first (8) bus of the power source and the second (3) current output of the first (1) input differential voltage-current converter connected to the second (5) current output of the second (6) input differential voltage-current converter and second (11) mouth devices, and the second (6) input differential voltage-current converter includes a third (20) and fourth (21) input transistors, the bases of which are connected to the second group (22, 23) of the antiphase inputs (22), (23) of the device, the emitter of the third (20) input transistor is connected to the second (16) bus of the power source through the third (24) reference current source, the emitter of the fourth (21) input transistor is connected to the second (16) bus of the power source through the fourth (25) reference current source, between emitters of the third (20) and fourth (21) input trans tori included a second (26) scaling resistor, characterized in that the first (17) and second (18) reference current sources are made in the form of controlled reference current sources with the corresponding control inputs (27) and (28), which are connected to the output of the cascade (29) for isolating the output common-mode voltage of the first (1) input differential converter “Voltage-current”, and the inputs of the cascade (29) for isolating the output common-mode voltage of the first (1) input differential voltage-current converter are connected to the corresponding first (2) and second (3) antiphase current outputs of the first (1) input differential voltage-current converter. 2. The multidifferential operational amplifier according to claim 1, characterized in that the third (24) and fourth (25) sources of the reference current of the second (6) input differential voltage-current converter are made in the form of controlled sources of the reference current with the corresponding control inputs ( 30) and (31), which are connected to the output of the cascade (29) for isolating the output common-mode voltage of the first (1) input differential voltage-current converter. 3. The multidifferential operational amplifier according to claim 1, characterized in that as the first (12), second (13), third (20) and fourth (21) input transistors use composite transistors in the form of field effect transistors, the sources of which correspond to emitters, drains to collectors, and gates to the bases of bipolar transistors. 4. The multidifferential operational amplifier according to claim 1 or 2, characterized in that the outputs (11) and (9) of the device are connected to the inputs of an additional differential buffer stage (32).

Images