RU2385542C2 - Receiving device of noise-like signals - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: invention may be used to receive information along communication channels in space and surface systems using noise-like signals (NLS). Receiving device for noise-like signals comprises unit of linear part, matched filter, summator, delay line, detector, switch, support generator, solver, synchroniser and separation circuit.

EFFECT: increased distance of consistent information reception.

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Description

The proposed device relates to the field of radio engineering and can be used to receive information via communication channels in space and ground systems using noise-like signals (SHPS).

Known receiving devices SHPS, built on the basis of matched filters or multi-channel correlators.

The search time in such devices is commensurate with the period of the used binary sequence. However, to implement such receiving devices in practice at large signal bases is a very difficult task (see Theory and application of pseudorandom signals, Alekseev A.I., Sheremetyev A.G., Tuzov G.I., Glazov B.I., M., Science, 1969

It is also known receiving device ShPS, and.with. No. 1109915 of the USSR, containing a linear path, a matched filter, a quadrature multiplier, an integrator, a block for selecting and memorizing per clock, a low-pass filter, a controllable phase shifter, an envelope detector, a weight adder, and a decider.

The disadvantage of this device is that if there is structural interference at its input, the noise immunity drops sharply with respect to other types of interference, and when a sufficiently high level of this interference occurs, communication breakdown occurs.

Closest to the technical nature of the claimed device is a device with a phase-shifted signal described in the book of L.E. Varakin Communication system with noise-like signals, M., Radio and communications, 1986, Fig. 1.76, p.16, adopted as a prototype .

Figure 1 shows the functional diagram of the device of the prototype, where the notation is introduced:

1 - mixer;

2 - intermediate frequency amplifier (UPCH);

3 - matched filter;

4 - a decisive device;

5 - recipient of information;

6 - local oscillator;

7 - synchronizer.

The prototype device contains a series-connected mixer 1, UPCH2, a matched filter 3, a resolver 4, an information receiver 5, serially connected synchronizer 7, a local oscillator 6, the output of which is connected to the second input of the mixer 1, the second output of the synchronizer 7 is connected to the second input of the resolver 4, and the input of the synchronizer 7 is connected to the output of the matched filter 3.

The prototype device operates as follows.

The signal received at the receiving antenna is fed to the input of the mixer 1, where it is transferred using the local oscillator 6 to the intermediate frequency, amplified in UPCH2 and processed by the matched filter 3 (minimized). The signal in the form of convolutions from the output of the matched filter 3 is fed to the input of the synchronizer 7 and to the second input of the resolver 4. The synchronizer 7 searches for the phase-shifted (FM) signal in frequency and time and controls the operation mode of the resolver 4.

To search for the FM signal by frequency, the synchronizer 7 rebuilds the local oscillator 6.

After the search and entering synchronism at the output of the decider 4, an information sequence appears in the form of binary characters that are transmitted to the recipient of information 5.

To simplify the functional diagram of the prototype device, the mixer 1, UPCH2 and local oscillator 6 are combined into one block and are indicated by the block of the linear part 8.

A simplified functional diagram of the prototype device is shown in figure 2, where

3 - matched filter;

4 - a decisive device;

5 - recipient of information;

7 - synchronizer;

8 - block linear part.

The disadvantage of the prototype device is the small range of reliable reception of information.

To eliminate this drawback, an adder is connected in series to the device containing the linear part block, the input of which is the input of the device, a matched filter, a deciding device and a synchronizer, the second output of which is connected to the second input of the block of the linear part; a delay line whose output is connected to the input of the matched filter; a detector, the output of which is connected to the input of the resolving device, and the input of the detector is connected to the output of the matched filter; a key whose output is connected to the second input of the adder, the first input of which is connected to the output of the block of the linear part, and the first signal input of the key is connected to the output of the delay line; the reference generator and the allocation circuit, the output of which is the output of the device, while the output of the reference generator is connected to the third input of the allocation circuit and to the first input of the synchronizer, the second input of the synchronizer is connected to the output of the resolver, the first output of the synchronizer is connected to the first input of the selection circuit, the second output the synchronizer is connected, in addition, to the second controlled input of the key, and the output of the block of the linear part is connected, in addition, to the second input of the comparison circuit.

Figure 3 shows the functional diagram of the proposed device, where indicated:

3 - matched filter;

4 - a decisive device;

7 - synchronizer;

8 - block linear part;

9 - adder;

10 - delay line;

12 - detector;

13 - key;

15 - reference generator;

16 is a selection scheme.

The proposed device contains a series-connected block of the linear part 8, the adder 9, the delay line 10, the matched filter 3, the detector 12, the output of which is connected to the input of the resolving device 4, the output of which is connected to the second input of the synchronizer 7, and also a reference generator 15, the output of which connected to the first input of the synchronizer 7 and to the third input of the allocation circuit 16, the first input of which is connected to the first output of the synchronizer 7, and the second input of the allocation circuit 16 is connected to the output of the block of the linear part 8, the output of the circuit is highlighted 16 is the output of the device, and the key 13, the first signal input of which is connected to the output of the delay line 10, and the output of the key 13 is connected to the second input of the adder 9, while the second output of the synchronizer 7 is connected to the second controlled input of the key 13 and to the second input of the block linear part 8.

The proposed device operates as follows.

The signal received at the receiving antenna is fed to the input of the block of the linear part 8, consisting of a mixer, an intermediate frequency amplifier, and a local oscillator, where it is transferred to the intermediate frequency, amplified in the intermediate frequency amplifier and fed to the first input of the adder 9, the output of which is input delay lines 10.

In the near zone of the receiver from the transmitter (zone of reliable reception of information), the synchronizing signal is received when the transmitter emits during time T, where T is the duration of the synchronizing signal.

The transmitter emits n repeats of the clock signal, as shown in FIG.

The clock signal received during time T from the output of the delay line 10 is fed to the inputs of the matched filter 3, detector 12, and the resolver 4, from the output of which the signal is fed to the second input of the synchronizer 7 to start it. From the first output of the synchronizer 7, the signal is supplied to the first input of the allocation circuit 16 for synchronization.

To ensure the quality of signal reception with a probability of 10 ^-2 , the necessary signal-to-noise ratio should be at least 6 dB (near zone).

To ensure detection of a signal with a probability of 10 ^-4 , the necessary signal-to-noise ratio should be at least 12 dB (far zone).

To equalize these relations, a signal is needed from the output of the delay line 10, where the signal is delayed exactly by the duration of the information signal T and through the public key 13 is fed to the second input of the adder 9, where it is summed up with the synchronizing signal received during the time T ₂ (repeat), see 4, and so it will be summarized until a signal (convolution) appears on the output of the matched filter 3, which is detected in the detector 12 and through the resolving device 4 and synchronizer 7, from the second output is fed to the second controlled input key 13, closing it, thereby stopping the accumulation of the information signal and stopping the local oscillator tuning in the block of the linear part 8.

The clock accumulates until a signal is detected in time (n · T), then the key 13 is opened and the search cycle is repeated.

From the output of the block of the linear part 8, the signal also goes to the second input of the allocation circuit 16, which consists of a correlator and a phase detector, where it is processed and fed to the output in the form of binary information to the consumer.

The signal from the output of the reference generator 15 is fed to the first input of the synchronizer 7, for the formation of synchronizing signals, and to the third input of the allocation circuit 16, for the formation of control signals of the correlator.

Figure 5 shows one example of the implementation of the synchronizer 7 (control circuit), where indicated:

7.1 - frequency divider - divides the frequency of the signal of the reference generator in such a way that its period is equal to τ, where τ is an elementary premise.

7.2 - frequency divider - divides the frequency of the signal so that its output period is 1 (the period of one signal sending).

7.3 - frequency divider - divides the frequency of the signal from the output of the divider 7.2 so that the output signal is equal to (n · T) - the duration of n signal transmissions.

7.4 - binding trigger, from the output of which the key 13 is locked for a time T and the work of the local oscillator of the linear part 8 is stopped.

7.5 - binding trigger, the output of which the signal synchronizes the operation of the signal allocation circuit 16.

Figure 6 shows one of the options for implementing the solver 4, where indicated:

4.1 - scheme of the formation of the threshold;

4.2 - threshold device.

Claims (1)

A noise-like signal receiving device comprising a linear part block, the input of which is the device input, a matched filter, a resolver and a synchronizer, the second output of which is connected to the second input of the linear part block, characterized in that the adder is connected in series and a delay line is connected, the output of which is connected with the input of the matched filter, a detector whose output is connected to the input of the resolving device, and the input of the detector is connected to the output of the matched filter; a key whose output is connected to the second input of the adder, the first input of which is connected to the output of the block of the linear part, and the first signal input of the key is connected to the output of the delay line; the reference generator and the allocation circuit, the output of which is the output of the device, while the output of the reference generator is connected to the third input of the allocation circuit and to the first input of the synchronizer, the second input of the synchronizer is connected to the output of the resolver, the first output of the synchronizer is connected to the first input of the selection circuit, the second output synchronizer, in addition, is connected to the second controlled input of the key, and the output of the block of the linear part is connected, in addition, to the second input of the allocation circuit.

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