RU42375U1 - DEVICE FOR RECEIVING BROADBAND SIGNALS IN SPACE COMMUNICATION SYSTEMS - Google Patents

Abstract

The invention relates to radio communications technology and can be used for receiving information on space communication channels with broadband signals. The technical result is to increase the speed of the device with a long duration of the information signal. This is achieved by the fact that four reference signal generators 3.3-3.6, four multipliers 1.3-1.6, four band-pass filters 7.3-7.6 and the message of threshold blocks 10.1-10.6 are introduced into the receiving device. In addition, the second phase shifter 12, the first 14 and second 15 keys, three adders 13, 16 and 17, a high-frequency amplifier 2, a mixer 4, an intermediate-frequency amplifier 5, a local oscillator 6, as well as the first 8 and second 9 comparison schemes.

Description

The proposed device relates to techniques for radio communications and can be used to receive information on space communication channels with broadband signals.

Known searchless devices built on the basis of matched filters or multi-channel correlators. The signal search time in such devices is commensurate with the period of the used binary sequence. However, to implement such receivers in practice at large signal bases is very problematic ("Theory and Application of Pseudorandom Signals" A.N. Alekseev, A.G. Sheremetyev, G.Y. Tuzov, B.I. Glazov, M., "Science ", 1969).

A receiver device for broadband signals according to AS 1109915, USSR, is also known, which contains a linear path, a matched filter, a quadrature multiplier, an integrator, a block for selecting and storing per clock, an LPF, a controlled phase shifter, an envelope detector, a weight adder, a comb filter, and a giving birth block .

The disadvantage of this device is that in the presence of structural interference at its input, noise immunity sharply decreases with respect to other types of interference, and with a sufficiently high level of structural interference, communication breakdown occurs.

The closest in technical essence to the proposed one is a receiving device for AS 3000046, taken as a prototype.

The functional diagram of the prototype device is shown in

figure 1, where indicated:

1, 2 - Vervius and the seas multipliers;

3 - shaper orthogonal pseudo-random sequence FOPP);

4 - generator reference pseudorandom sequence (GOPP);

6 - phasing device;

6 - synchronization device;

7, 8 - the first and second band-pass filters;

9 - phase detector.

The prototype device contains a series-connected pore multiplier 1 and a first band-pass filter 7, the output of which is connected to the first input of the phase detector 9, serially connected to the second multiplier 2 and a second band-pass filter 8. the output of which is connected to the second input of the phase detector 9, the output of which is device output. The output of the synchronization device 6 is connected to the first inputs of FOPP 3 and GOPP 4, the outputs of which are connected to the second inputs of the first 1 and second 2 multipliers, respectively. In this case, the first and second outputs of the phasing device 6 are connected to the second inputs of the FOPP 3 and GOPP 4, respectively. In addition, the first inputs of the first 1 and second 2 multipliers are connected to the input of the synchronization device 6 and are the input of the device.

The prototype device operates as follows.

The received signal is fed to multipliers 1 and 2. In multiplier 1, the received signal is multiplied by the binary pseudo-random sequence that produces

FOPP 3. The signal from the output of the multiplier 1 is fed to a band-pass filter 7, which emits oscillations in the carrier frequency of the signal. In the multiplier 2, the received signal is multiplied by a binary pseudo-random sequence that the GOPP 4 generates. The signal from the output of the multiplier 2 goes to a band-pass filter 8, which emits a phase-controlled oscillation of the carrier frequency of the signal. Phasing device 5 provides communication in the phase phase of the output sequences FOPP 3 and GOPP 4, corresponding to the communication so phase of the sequences of the transmitter. The binary pseudo-random sequences generated by the generators in the receiver are synchronized with the binary pseudo-random sequences of the received signal using the synchronization device 6. As the synchronization device 6, known synchronization devices can be used to ensure that the local signals of the receiver are synchronized with the main beam of the received multipath signal based on the analysis of the mutual function correlations of received and local signals.

Oscillations of the carrier frequency from the outputs of the bandpass filters 7 and 8 are fed to a phase detector 9, which measures the information phase difference between them.

The disadvantages of the prototype device is that the signal search takes a lot of time, especially with a long duration of the information signal.

To eliminate this drawback in a device for receiving broadband signals containing a series-connected first generator of reference signals (GOS), a multiplier and a bandpass filter (PF), series-connected second

GOS, multiplier and PF, and the inputs of the first and second GOS are connected to the output of the synchronizer, the inputs of both multipliers are interconnected, and the first phase shifter, according to the utility model, four GOS, four multipliers, four PF and six threshold blocks are introduced, the output of each which is connected to the corresponding input of the third adder, the output of which is connected to the first input of the synchronizer, in addition, the second phase shifter and the first key are connected in series, the output of which is connected to the second input of the first a matcher, as well as a second switch, the output of which is connected to the second input of the second adder, the first and second comparison circuits, series-connected high-frequency amplifier (UHF), a mixer and an intermediate frequency amplifier (UPCH), the output of which is connected to the inputs of all multipliers, and a local oscillator, the output of which is connected to the second input of the mixer, the input of the UVR is connected to the receiving antenna, while the inputs of the GOS from the third to the sixth are connected to the input of the second GOS, the outputs of the GOS from the third message are connected to the second inputs respectively the third to sixth multipliers, the outputs of the Third and fourth multipliers are connected to the inputs of the corresponding threshold blocks, the output of the second PF connected to the first input of the first comparison circuit, the output of which is connected to the second input of the synchronizer, and the output of the fourth PF connected to the second input of the first comparison circuit in addition, the output of the fifth multiplier is connected to the input of the first phase shifter and through the first adder and fifth 36 connected in series with the inputs of the fifth threshold block and the first inputs of the second Hema comparison, the output of the sixth multiplier

connected to the input of the second phase shifter and through the second adder and the sixth PF connected in series with the input of the sixth threshold block and the second input of the second comparison circuit, the output of which is connected to the third input of the synchronizer, the third output of which is connected to the control inputs of the first and second keys, the second output of the synchronizer connected to the input of the local oscillator, in addition, the outputs of the first and second PF are connected to the inputs of the corresponding threshold blocks.

Functional diagram of the proposed device is shown in figure 3, where indicated:

1 ₁ -1 ₆ - the first - sixth multipliers;

2 - high frequency amplifier (UHF);

3 ₁ -3 ₆ - first - sixth reference signal generators (GOS);

4 - mixer;

5 - intermediate frequency amplifier (UHF);

6 - local oscillator;

7 ₁ -7 ₆ - the first - sixth band-pass filters;

8, 9 - the first and second comparison schemes;

10 ₁ -10 ₆ - the first - sixth threshold blocks;

11, 12 - the first and second phase shifters;

13, 16, 17 - the first, second and third adders;

14, 15 - the first l of the second keys;

18 - synchronizer.

The proposed device contains a series-connected UHF 2, mixer 4 and UPCH 5, as well as a local oscillator 6, the output of which is connected to the second input of the mixer 4, while

UHF input 2 is connected to the receiving antenna. The output of the UPCH 5 is connected to the first input of each of the six multipliers 1 ₁ -1 ₆ , the second input of each of which is connected to the output of the corresponding GOS 3 ₁ -3 ₆ , the inputs of which are interconnected. The output of each of the four multipliers 1 ₁ -1 ₄ through the corresponding band-pass filter 7 ₁ -7 _{4 is} connected to the input of the corresponding threshold block 10 ₁ -10 ₄ , the output of each of which is connected to the corresponding input of the third adder 17. The outputs of the second 7 ₂ and the fourth 7 ₄ bandpass filters are connected to the corresponding inputs of the comparison circuit 8. The output of the fifth 1 ₅ multiplier through a series-connected first phase shifter 11 and the second key 15 is connected to the second input of the second adder 16, as well as to the first input of the first adder 13, the output of which through the fifth bandpass filter 7 ₅ and the fifth threshold block 10 _{5 is} connected in series with the corresponding input of the third adder 17. The output of the sixth multiplier 1 ₆ through the second phase shifter 12 and the first key 14 connected in series is connected to the second input of the first adder 13, and also the first input of the second adder 16, whose output is series connected through the bandpass filter 7 news ₆ and sixth threshold unit 10 ₆ is connected to the corresponding input of the third adder 17, whose output is connected to the ne vym input synchronizer 18, whose output is the first output device. The outputs of the fifth 7 ₅ and sixth 7 ₅ bandpass filters are connected to the corresponding inputs of the second comparison circuit 9, the output of which is connected to

the third input of the synchronizer 18, the second input of which is connected to the output of the first comparison circuit 8. The second output of the synchronizer 18 is connected to the input of the local oscillator 6, the third output of the synchronizer 18 is with the control inputs of the first 14 and second 15 keys, the fourth output is with the inputs of the GOS 3 ₁ - 3 ₆ . The proposed device operates as follows. The signal received by the receiving antenna is fed to UHF 2, where it is amplified to the required value and fed to the mixer 4, to the second input of which the local oscillator signal 6. The local oscillator 6 (frequency tuning) is controlled by the synchronizer 18 - for the case when information is transmitted on more than one carrier frequency (UHF 2, mixer 4 and local oscillator make up the external receiver head (VGP), which is structurally located with the receiving antenna. In UHF 5, the signal is amplified at an intermediate frequency to the required Next, the signal is fed to the first inputs of six multipliers 1 ₁ -1 ₆ , the second inputs of which are fed signals with the corresponding GOS 3 ₁ -3 _{6. The} time shift between the reference signals is one clock cycle.The results of multiplying the received signal with the reference are filtered in blocks 7 ₁ -7 ₆ , and then evaluated by the level in the threshold blocks 10 ₁ -10 ₆ , summed up in the third adder 17 and served in the synchronizer 18. The keys 14 and 15 are closed, so all the tin channels of signal detection are in the same state.

By sequentially shifting the reference signal by 6τ, the device searches until a signal appears at the output of one of the six threshold blocks 10 ₁ -10 ₆ . When a signal appears

tuning stops and, by shifts within 6τ, the detected signal is sent to the central - third channel. After confirming three consecutive signals in the third channel, a signal is generated about the detection of a sync sequence component (SP); for this, reference signals of the SP are shifted to multipliers 1 ₂ and 1 ₄ shifted relative to the central (third) channel by + τ / 2 and -τ / 2, respectively . When my levels of convoluted signals from filters 7 ₂ and 7 ₄ will depend on the degree of discrepancy in the delay of the reference signals and the received signal. In the case of their exact coincidence at the output of the comparison circuit 8, the signal is absent. With a mismatch, the signal level in one of the channels will increase, in the other it will decrease. At the output of the comparison circuit 8, a detuning signal will appear, which changes the clock frequency of the reference oscillators 3 ₁ -3 ₆ until the detuning signal hits, that is, until the clock frequencies of the received signal and the reference signal are equal.

At the same time, in the first channel, the reference signals of the joint venture are replaced by a signal of the information sequence (II), and the search for the information component begins. After the detection of IP in the block 10 ₁ signals of IP, the synchronizer 18 generates a detection signal. In channels 5 and 6, a signal is extracted. At the command of the information detection signal (SDI) supplied from the synchronizer 18, the keys 14 and 15 are opened. At the same time, the signals of the CE and II components are turned on to the filters 7 ₅ and 7 ₆ , rotated 90 ° relative to each other and summed together. So in one of the filters 7 ₅ ,

7 ₆ during the information sending there will be a double level of the minimized signal, in another filter - the level of non-coiled noise.

In the comparison circuit 9, the signals from the outputs of the filters 7 ₅ and 7 _{6 are} compared with each other and an information signal appears at the output of the comparison circuit 9, which enters the synchronizer 18, where it is normalized by level and duration, then fed to the output of the device.

Thus, the proposed utility model allows to reduce the search time of the received signal in this case by a factor of ten compared with the prototype device.

The synchronizer 18 can be built, for example, according to the scheme shown in figure 2, where it is indicated:

18.1 - generator of clock pulses;

18.2 - block formation of a temporary shift of the SRP;

18.3 - block fine tuning;

18.4 - signal analysis block;

18.5 - switching unit copies of the SRP;

18.6 - block formation of information impulses. The synchronizer 18 contains a serially connected clock shaper 18.1, a signal analysis unit 18.4 and a copy switching unit PSP 18.5, the first output of which is connected to the first input of the time shift generation block PSP 18.2, the second input of which is connected to the second output of the clock shaper 18.1, and the third input block 18.2 is connected to the output of the fine tuning block 18.3, the first input of which is connected to the first input of the forming unit

information pulses 18.6 and the first output of the shaper 18.1.

Synchronizer 18 operates as follows,

The clock generator 18.1 operates in the mode of a clock generator, which are fed to one of the inputs of block 18.2, in which six PSEs are formed, shifted by a clock relative to each other. At one of the inputs of block 18.3, clock pulses are received, and at the other input, a signal from the comparison circuit 8, in block 18.3, fine tuning is performed with respect to the delay. In block 18.4, counters are used to confirm three consecutive signals, which then turn on block 18.3 and stop delay tuning.

In block 18.5, the reference signals are switched for key management. 14 and 15. In block 18.6, information pulses are generated and output to the device output.

The construction of the remaining blocks and nodes is well known and widely published in the technical literature.

Claims (1)

A device for receiving broadband signals in space communication systems, comprising a series-connected first generator of reference signals (GOS), a multiplier and a bandpass filter (PF), a series-connected second GOS, a multiplier and a PF, the inputs of the first and second GOS are connected to the output of the synchronizer, the inputs of both multipliers are interconnected, as well as the first phase shifter, characterized in that four GOS, four multipliers, four PF and six threshold blocks are introduced, the output of each of which is connected to the corresponding the corresponding input of the third adder, the output of which is connected to the first input of the synchronizer, in addition, the second phase shifter and the first key are connected in series, the output of which is connected to the second input of the first adder, as well as the second key, the output of which is connected to the second input of the second adder, the first and second comparison circuits connected in series to a high-frequency amplifier (UHF), a mixer and an intermediate-frequency amplifier (UHF), the output of which is connected to the inputs of all multipliers, as well as a local oscillator, the output of which the second is connected to the second input of the mixer, the input of the UHF is connected to the receiving antenna, while the GOS inputs from the third to the sixth are connected to the input of the second GOS, the outputs of the GOS from the third to sixth are connected to the second inputs of the corresponding third to sixth multipliers, the outputs of the third and fourth multipliers connected to the inputs of the corresponding threshold blocks, the output of the second PF connected to the first input of the first comparison circuit, the output of which is connected to the second input of the synchronizer, and the output of the fourth PF is connected to the second input the first comparison circuit, in addition, the output of the fifth multiplier is connected to the input of the first phase shifter and through the first adder and the fifth PF connected in series with the input of the fifth threshold block and the first input of the second comparison circuit, the output of the sixth multiplier is connected to the input of the second phase shifter and through the second the adder and the sixth PF - with the input of the sixth threshold block and the second input of the second comparison circuit, the output of which is connected to the third input of the synchronizer, the third output of which is connected to control inputs of the first and second keys, the second output of the synchronizer is connected to the input of the local oscillator, in addition, the outputs of the first and second PF are connected to the inputs of the corresponding threshold blocks.