RU2292582C1 - Information input device - Google Patents

Abstract

FIELD: computing equipment for connecting analog systems to digital computer machines.

SUBSTANCE: device contains analog key, commutators of upper and lower levels, level shift circuits, generator of step voltage, OR element, impulses generator, RS-trigger, counter, AND elements of first and second groups, connected to output of device. Additionally introduced to device are mono-stable multi-vibrator and four generators, as a result of which number of counts is decreased time interval between which is less than time of relaxation of mono-stable multi-vibrator.

EFFECT: decreased excessiveness of information with preservation of restoration precision.

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Description

The invention relates to the processing of digital data using electronic devices, namely to computer technology, and can be used to interface analogue systems of measurement, control and management with digital computers.

Known devices for entering information (USSR author's certificate No. 1083177, 1151946, class G 06 F 3/05) containing amplitude discriminators, logical elements AND, OR, triggers and counters.

The disadvantage of these devices is their complexity due to the fact that the number of amplitude discriminators in them is equal to the number of quantization levels.

Closest to the technical nature of the claimed device is a "Device for entering information" (USSR Author's Certificate No. 1305695, class G 06 F 13/00, 1987).

The device contains a controlled pulse generator, a counter, AND elements, an OR element, a delay element, an analog key, a comparator unit, a control command generator, inputs of a controlled pulse generator are the control inputs of the device, the clock output of a controlled pulse generator is connected to the counter input of the counter, the outputs of which are connected to the first inputs of the group of AND elements, the outputs of which are the first group of information outputs of the device. The output of the OR element is connected to the second inputs of the AND elements and through the delay element with the counter reset input, the information input of the analog key is the information input of the device, and the control input is connected to the installation output of the controlled pulse generator, the output of the analog key is connected to the input of the comparator unit, the outputs of which are connected to the inputs of the control command generator. The device also contains a step voltage generator, blocks for setting initial voltage displacements, the first and second inputs of a step voltage generator are connected to the corresponding outputs of the control command generator and inputs of an OR element, the output of the step voltage generator is connected to inputs of blocks for setting the initial biases, the outputs of which are connected to a group of inputs block of comparators, the group of outputs of the step voltage generator is the second group of information outputs of the device.

The control command generator contains two NOT elements and two RS-flip-flops, the trigger outputs are the first and second outputs of the former respectively, the output of the first and second elements are NOT connected to the inputs of the “0” set, respectively, of the first and second triggers, the input of the first element and the installation input in "1" of the second trigger are combined, the installation input in "1" of the first trigger, the inputs of the elements are NOT inputs of the former.

гарантирующих требуемую точность восстановления исходного сигнала.The device is sufficiently simple due to the use of three amplitude discriminators. However, its disadvantage is the large redundancy of the recorded information, since the amplitude reports over time in areas with a rapid rise in the input voltage front are separated from each other at distances shorter than required by Kotelnikov’s theorem

guaranteeing the required accuracy of restoration of the original signal.

The aim of the invention is to reduce the amount of recorded information while maintaining the accuracy of reproduction.

This goal is achieved by the fact that in the device for inputting information containing an analog switch 2, the input of which is the information input of the device 1, and the output is connected to the inputs of the comparators of the lower 3 and upper 4 levels, the second inputs of which are connected to the shift schemes of levels 9, 10 to the output of the step voltage generator 8, the summing and subtracting inputs of which are connected to the inputs of the element OR 13, the pulse generator 14, the output of which is connected to the first input of the element And 15, the second input of which is connected to the direct output m of RS-flip-flop 16, and the output is connected to the counting input of the counter 17, the bit outputs of which are connected to the first inputs of the AND elements of the second group 18, the outputs of which are the second outputs of the device 19, while the output of the delay element 23 is connected to the installation input of the counter 17, four shapers 6, 7, 21 and 22, a single vibrator 20 and elements I11 of the first group, the first inputs of which are connected to the information outputs of the step voltage generator 8, and the outputs are the first output of the device 12, and the second inputs of the elements I11 are connected are Din to the output of the former 21 and to the input of the delay element 23, the output of which is also connected to the input S of the unit in the RS-flip-flop unit 16, the input R of which is set to "0" which is connected to the output of the former 22 and to the second inputs of the elements And 18 of the second group, the outputs of which are the second output of the device 19, the output of the upper level comparator 4 is connected through the driver 7 to the summing input of the step voltage generator 8, the subtractive input of which is connected to the output of the driver 6 connected to its input through the inverter 5 with the output to a lower level apparatus 3, while the output of the OR element 13 is connected to the input of a single-shot 20, the output of which is connected to the inputs of the formers 21 and 22.

In Fig.1 presents a functional diagram of a device for entering information, in Fig.2 and Fig.3 are timing diagrams explaining its operation.

A device for entering information works as follows.

In the initial state, the analog switch 2 is open, the RS-flip-flop 16 and the counter 17 are zeroed, the voltage level is zero at the output of the step voltage generator, so that the potential is at the second input of the comparator 3, and the potential at the second input of the comparator 4 is determined by the number of directly biased diodes in level 9 shift scheme.

Assume that the input voltage at input 1 rises from zero. As soon as this voltage exceeds the potential level of the second input of the comparator 4, a high potential will appear at its output. After (diagram 2a) the passage of the shaper 7, which is a leading edge allocation circuit (diagram 1b - U ₆ ), a short pulse will appear that will launch the one-shot 20 through the OR 13 element. At the same time, this pulse will arrive at the summing input of the step generator voltage 8. The potential at the output of the generator 8 will rise by one step, so that the potential difference U ₂ -U ₁ = ΔU appears at the output of the level 9 and 10 shift circuits, while the voltage U ₁ will be applied to the second input of the lower level comparator 3, and on voltage U ₂ - to the second input of the upper level 3 comparator, so that the input voltage level is within the quantization level ΔU = U ₂ -U ₁ . With a further increase in the input voltage, it will reach the level of U ₂ , as a result of which the high potential will again appear at the output of the upper level comparator, which through the former 7 will go to the summing input of the step voltage generator 8, as a result of which the potential at its output will increase by one stage and so on. The process will continue until an increase in the input voltage is observed, so that at the second inputs of the comparators 3 and 4 potentials U _i , U _{i + 1} will be observed, which always differ by ΔU = U _{i + 1} -U _i (Fig. 2a). As soon as the input voltage reaches a maximum and begins to decrease, when the level of the comparator of the lower level 3 is crossed, a low potential will appear at its output, which will go through the inverter 5 and the driver 6 (representing a trailing edge selection circuit, U7 in Fig.2b) to the subtracting input a step voltage generator 8, as a result of which the potential at its output decreases by one step. The process will be repeated in the same sequence until the input voltage decreases.

The diagram of FIG. 2a shows a voltage diagram at the output of a step voltage generator.

Upon receipt of the leading edge of the pulse from the output of the driver 7 and the OR element 13 to the input of the one-shot 20, the latter is triggered and a high potential appears at its output (diagram U ₂₀ in figure 2). The time spent in the relaxation period is determined by its parameters τ _ρ = τ _n , i.e., the pulse duration at its output determines the period of time during which it is not sensitive to input pulses. At the end of the relaxation period at the output of the one-shot 20, the voltage returns to "0". At the output of the shaper 21, which is a trailing edge allocation circuit, a positive pulse appears that arrives at the second inputs of the I11 elements of the first group, and the potentials from the information outputs of the step voltage generator 8 go to the first output of the device 12, forming a binary amplitude code. At the same time, a positive pulse from the output of the shaper 21 enters through the delay element 23 to the installation input 12 of the counter 17 and to the S-installation input in the “1” RS-flip-flop 16, which goes into the second stable state, while a high output appears on its direct output the potential that opens the element And 15. The pulses of the generator 14 begin to flow to the counting input of the counter 17, filling it. When the next pulse arrives from the output of the OR 13 element, the one-shot 20 is triggered, and a high potential appears at its output, which, through the driver 22, which is a front edge allocation circuit, transfers the RS trigger at the input R to its initial state. Element I15 closes, stopping the supply of pulses to the counting input From the counter 17. At the same time, this pulse from the output of the shaper 22 goes to the second inputs of the elements And 18 of the second group, and high potentials from the discharge outputs of the counter 17 go to the output of the device 19, forming a binary time code.

The positive effect of the implementation of the proposed device for entering information is illustrated by the diagram in figure 3.

The device implements a two-coordinate method for measuring the magnitude of the amplitude and time.

где ΔF_C - верхняя граничная частота спектра сигнала, что гарантирует наивысшую точность восстановления. На пологих участках входного сигнала время пересечения двух смежных уровней U_i и U_i+1 может значительно превышать τ_ρ. В этом случае запускается механизм управления, при котором задним фронтом одновибратора 20 (схема выделения заднего фронта 21) опрокидывается RS-триггер 16, который открывает элемент И15, и импульсы с генератора 14 заполняют счетчик 17. Этот процесс продолжается до очередного срабатывания компаратора 4.The magnitude of the voltage is measured at the time of the return of the single vibrator 20 to its original state (on the trailing edge). At this point in time, the I11 elements of the first group open, and the voltage from the discharge outputs of the reversible counter and the step voltage generator 8 is supplied to output 12, forming an amplitude code. The pulses coming from the output of the comparator 4 (during the reverse process - comparator 3) through the forming unit 7 (6) and the OR13 element during the relaxation period of the single vibrator 20 at its input will be absorbed without causing it to operate. For signals with a limited spectrum, the relaxation time is chosen equal to

where ΔF _C is the upper cutoff frequency of the signal spectrum, which guarantees the highest restoration accuracy. In the flat sections of the input signal, the intersection time of two adjacent levels of U _i and U _{i + 1} can significantly exceed τ _ρ . In this case, the control mechanism starts, in which the RS-flip-flop 16, which opens the I15 element, is tipped over by the trailing edge of the one-shot 20 (the trailing edge 21 allocation circuit), and the pulses from the generator 14 fill the counter 17. This process continues until the next operation of the comparator 4.

The front edge of the triggered single-shot 20 (from the output of the shaper 22) will return the trigger 16 to its original state. At the same time, the content of the counter 17 through the elements And 17 of the second group will appear on the second output of the device 19, forming a binary time code. The time between two successive trips of the comparator will be

where F ₂ is the pulse repetition rate of the generator 14,

n is the number of pulses accumulated in the counter 17 during the time between two operations of the comparators.

Thus, the binary expression of the number n is registered at the second output of the device 19.

Claims (1)

A device for inputting information, containing an analog key, open in the initial state, the input of which is the information input of the device, and the output is connected to the inputs of the lower and upper level comparators, to the second inputs of which a step voltage generator output is connected through the level shift circuits, which sums and subtracts the inputs which is connected to the inputs of the OR element, a pulse generator, the output of which is connected to the first input of the And element, the second input of which is connected to the direct output of the RS-trigger, and the output under is connected to the counter counter input, the bit outputs of which are connected to the first inputs of the AND elements of the second group, the outputs of which are the second outputs of the device, while the output of the delay element is connected to the installation input of the counter, characterized in that the first and third formers of the trailing edge are inserted into it pulse, the second and fourth formers of the selection of the leading edge of the pulse, one-shot and elements And the first group, the first inputs of which are connected to the bit information outputs of the generator steps voltage, and the outputs are the first outputs of the device, the output of the upper level comparator through the first driver is connected to one input of the OR element, to the other input of which the inverter and the second driver are connected to the output of the lower level comparator, the output of the OR element is connected to the input of a one-shot connected to its output with the inputs of the third and fourth shapers, while the output of the third shaper is connected to the second inputs of the elements of the first group and the input of the delay element, and the output of the fourth the shaper is connected to the second inputs of the And elements of the second group and to the R-input of the RS-flip-flop set to zero, the S-input of the unit to which is connected to the output of the delay element.

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