RU2234729C2 - Random signals discriminator - Google Patents

Abstract

FIELD: specialized data-processing means engineering.

SUBSTANCE: device has multiplexer, ADC, multiplier, collecting adder, block for dividing by constant coefficient, controlling block.

EFFECT: simplified device construction.

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Description

The invention relates to specialized computing tools and is used for a comparative analysis of random processes, in particular for solving problems of discrimination of random signals on energy grounds.

Known discriminator of random signals containing two input blocks, a delay line, a subtraction block, a quadrator and an averaging block, the output of which is the output of the discriminator, the first and second information inputs of which are the inputs of the first and second input blocks, the output of the first one is connected to the first input a subtraction unit, to the second input of which the output of the second input block is connected through a delay line, the output of the subtraction unit through a quadrator is connected to the input of the averaging unit [Mirsky G.Ya. Hardware-based characterization of random processes. - M .: Energy, 1972, p. 152, fig. 4-156].

The disadvantage of this device is the difficulty of implementation, which is associated with the need to use two input blocks with identical characteristics.

The closest in technical essence to the claimed discriminator is a random signal discriminator, consisting of two analog-to-digital converters (ADC), a delay line with (m-1) taps, m multipliers, m accumulators and a recorder, the first inputs of m multipliers being combined and connected to the output of the first ADC, the second input of the first of m multipliers is connected to the output of the second ADC, and the second inputs of the remaining (m-1) multipliers are connected to the corresponding (m-1) taps of the delay line, the input of which is connected to the output of the second ADC, the outputs of m multipliers are connected to the inputs of the corresponding m accumulating adders, the outputs of which are connected to the corresponding inputs of the recorder, the first and second information inputs of the discriminator are respectively the information inputs of the first and second ADCs [Gribanov Yu.I. et al. Automatic digital correlators. M .: Energy, 1971, p. 150, fig. 4-6].

The prototype discriminator is a parallel type correlator and discriminates random signals by calculating their cross-correlation function. In this case, the parameter that determines how much the signals differ is the correlation coefficient — a coefficient that determines the degree of statistical relationship (in a particular case). However, to calculate this coefficient, the mere ordinates of the cross-correlation function that the prototype calculates are not enough. The data obtained at the output of the prototype discriminator (the value of the cross-correlation function at zero shift) are used only as separate components, which, together with others, allow us to calculate the correlation coefficient. For this, it is still necessary to perform a number of operations, including calculating the values of the autocorrelation functions of each of the signals at a zero time shift, find their geometric mean and then take the ratio. Thus, when the task is not to determine the degree of statistical interconnection of process values, but the task is to compare random processes by energy properties, by what real impact they can have, the methods of correlation analysis are unreasonably complicated.

The lack of prototype functional complexity.

The technical result achieved by using the present invention is to simplify the discriminator.

The technical result is achieved by the fact that in the well-known random signal discriminator containing an ADC, a multiplier and an accumulating adder, the information input of which is connected to the output of the multiplier, the first input of which is connected to the ADC output, according to the invention, a multiplexer, a division unit and a control unit controlling and zeroing are introduced the inputs of which are the corresponding inputs of the discriminator, the first and second information inputs of which are respectively the first and second information inputs of multi a plexor whose output is connected to the ADC information input, whose clock input is connected to the clock output of the control unit, the address input of the multiplexer is combined with the mode input of the accumulating adder and connected to the mode output of the control unit, the second input of the multiplier is combined with its first input, and the output of the accumulating adder connected to the input of the division unit, the output of which serves as the output of the discriminator.

The invention is illustrated by functional diagrams.

Figure 1 shows the functional diagram of the discriminator of random signals; figure 2 is a functional diagram of a control unit 6.

The functional diagram of the discriminator (Fig. 1) comprises a multiplexer 1, ADC 2, a multiplier 3, a reversible accumulating adder 4, a division unit 5, and a control unit 6. The output of the multiplexer 1 is connected to the information input of the ADC 2, the input of which is connected to the combined inputs of the multiplier 3, the input of which is connected to the information input of the accumulating adder 4, the output of which is connected to the input of the division unit 5, the output of which is the output ΔD of the discriminator, the first X (t) and the second Y (t) information inputs of which are, respectively, the first and second information inputs of multiplexer 1, whose address input A is combined with the mode input U / D (Up / Down) of the reverse accumulating adder 4 and The key to modal output U / D control unit 6, the clock output CLK is connected to the clock input of the ADC 2, the SB control input of the control unit 6 is a triggering input of the discriminator and zeroing input RST of the control unit 6 - the input of the discriminator is zeroed.

The functional diagram of the control unit 6 (Fig. 2) contains triggers 7 and 8, a counter 9, a frequency divider 10, a clock generator 11, an element 2 OR 12, an element 2 AND 13 and an element 14 delay. The control input of the CO unit 6 is the S-input of the trigger 7, the output of which is connected to the D-input of the trigger 8, the clock input of which is combined with the first input of the element 2I 13 and connected to the output of the clock generator 11, the second input of the element 2I 13 is connected to the output of the trigger 8, the resetting input of which is combined with the first input of the element 2 OR 12 and is connected to the overflow output of the counter 9, the counting input of which is connected to the output of the element 2I 13, to which the combined inputs of the frequency divider 10 and the delay element 14 are connected, the outputs of which vlyayutsya respectively to regime U / D clock CLK and outputs of the control unit 6, input RST is zeroed which are combined second input element 2 or 12 and reset input of the counter 9.

The principle of operation of the discriminator is based on calculating the difference ΔD of the dispersions D _x and D _{y of} the random processes x (t) and y (t) under study. By the value of the difference ΔD, by how much it differs from zero, one judges the degree of difference (or vice versa, the degree of similarity) of the studied processes acting simultaneously. Given that the dispersion of a process from a physical point of view determines the average power of the process, then, therefore, the result of comparing random processes with the proposed method will determine how the energy properties of the processes differ: how much their average capacities differ.

The discriminator works (figure 1) as follows.

Random processes x (t) and y (t), stationary, ergodic and centered, are fed to the corresponding inputs of multiplexer 1, which alternately switches them to the input of ADC 2. At the same time, digital samples of x signals appear at the output of ADC 2 with clock frequency CLK ( t) and y (t). Moreover, if at the moment t _{n the} readout x (t _n ) was fixed at the output of the ADC 2, then at the next moment t _{n + 1} = t _n + Δt (Δt is the CLK clock period) at the output of the ADC 2 we will have the count y (t _{n + 1} ) = Y (t _n + Δt). Thus, each of the signals x (t), y (t) will be represented at the output of ADC 2 with a period of 2Δt, that is, twice as large as the clock period of ADC 2. As you can see, at the output of ADC 2 a sequence is formed that is formed by temporary compaction .

After the squaring operation in the multiplier 3, the digitized values of the samples x (t) and y (t) are sent to the input of the reversible accumulating adder 4, which switches from the addition mode to the subtraction mode and vice versa synchronously with multiplexer 1. When switching the adder 4 with a frequency , two times lower than the clock frequency of the ADC 2, the process of accumulating the result in its memory, that is, the current sum S _n , will be described by the expression

where S ₀ - the initial amount located at time t ₁ in the memory of the adder 4;

N is the number of samples in the sample, (N is an even number).

Grouping the terms in (1) by sign and introducing the sum symbol, we obtain a more compact and visual form of writing expression (1):

Assuming that S ₀ = 0, that is, before starting the calculations, zeroing the reversible accumulating adder 4 and multiplying the right side of expression (2) by a factor of 2 / N, which occurs in division block 5 (K = N / 2), we obtain the variance difference ΔD

or

ΔD = D _x -D _y .

Thus, at the output of the discriminator with the end of the observation interval, consisting of N samples, a binary code of ΔD value will be generated - estimates of the variance difference of the studied random signals x (t) and y (t).

Controls the calculation process ΔD block 6 (figure 2). According to the start-up pulse of CO, which is fed to its input of the same name, at the output of trigger 8, a high logic level is set synchronously with the front of the clock pulse, allowing the passage of clock pulses to the summing input of counter 9. The latter serves to set and count the duration of the observation interval - interval, during which takes samples of signals x (t) and y (t). The duration of the observation interval, which is expressed by the number of cycles, is determined by the conversion factor of the counter 9. The conversion factor is selected so that the overflow pulse at the output P of the counter 9 appears after the Nth clock pulse received at the output CLK of the control unit 6. With the occurrence of an overflow pulse, the triggers 7 and 8 are reset to zero and the CLK clock pulses cease, which leads to the end of the observation interval.

The CLK clock sequence after dividing by two in block 10 is used to switch the multiplexer 1 and the reverse accumulating adder 4. It is assumed that the signal at the output of the division block 10 is in the form of a “meander”, that is, it is a pulse sequence with a duty cycle of two. The CLK clock sequence must certainly be shifted relative to the control sequence at the output of block 10 towards the delay for a time not less than the time required to complete the transient processes when switching channels in the multiplexer 1. To ensure the specified delay, there is a delay element 14, the delay time of which when implemented devices in the TTLSh circuit technology basis should be (40-50) ns.

We also add that for clocking the reversible accumulating adder 4, it is advisable to use the clock sequence formed from the CLK sequence by shifting the latter by the time necessary to obtain a new count at the input of adder 4 after the arrival of the next clock pulse to the clock input of the ADC 2. The time required in this case the delay will be determined by the speed of the ADC 2 and the multiplier 3.

Claims (1)

A random signal discriminator containing an ADC, a multiplier and an accumulating adder, the information input of which is connected to the output of the multiplier, the first input of which is connected to the ADC output, characterized in that a multiplexer, a constant factor division block, and a control unit controlling and resetting the inputs are inserted into it which are the corresponding inputs of the discriminator, the first and second information inputs of which are respectively the first and second information inputs of the multiplexer, the output of which connected to the information input of the ADC, the clock input of which is connected to the clock output of the control unit, the address input of the multiplexer is combined with the mode input of the accumulating adder and connected to the mode output of the control unit, the second input of the multiplier is combined with its first input, and the output of the accumulating adder is connected to the input block division by a constant coefficient, the output of which serves as the output of the discriminator.

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