RU2223536C1 - Priority request servicing device - Google Patents

Abstract

FIELD: computer engineering; priority servicing of requests. SUBSTANCE: device that has request register, OR gate, AND gate, cascade of switches, and delay line incorporates reduced hardware amount and functions to search for higher- priority orders in each operating cycle. EFFECT: enhanced reliability and speed of device. 1 cl, 1 dwg

Description

 The invention relates to the field of computer technology, in particular to priority request servicing devices.

 A device for priority service requests [1], containing a register of applications, the inputs of which are connected to the information inputs of the device, priority registers, AND, OR elements, a counter whose outputs are connected to the first inputs of the comparison circuits, the outputs of which are connected to the first inputs of the elements And the first groups, and the counter counter input is connected to the output of the AND element, the first inverse of which is connected to the zero input of the control trigger, whose single input is connected through the first OR element to the input control devices with a single counter input, and a pulse generator.

 The disadvantage of this device is the availability of limited functionality, since with a large number of multi-priority applications, the waiting time for applications with low priority is very long, which in some cases is unacceptable and can lead to the loss of low-priority applications.

 The closest technical solution to the proposed one is a device for servicing queries [2], which allows to expand the functionality of the device by providing accounting for latency when servicing queries and containing a register of applications, priority registers made in the form of summing counters, two groups of elements AND, two groups elements OR, counter, pulse generator and frequency divider.

 The disadvantage of this device is the low speed, high complexity and, as a consequence, low reliability.

 The purpose of the invention is to increase the reliability and speed of the device by reducing its hardware composition and improving control over its operation.

This goal is achieved by the fact that in the device priority service requests containing a register of requests, the unit inputs of the bits of which are connected to the information inputs of the device, and the outputs are connected to the inputs of the OR element, the output of which is connected to the first input of the element And, the second input of which is connected to the permission line accepting the request, and the output of the AND element is connected to the first key of the key cascade, its inputs are connected to the outputs of the request register, the first output corresponding to a certain priority is connected to ulation input of the next key and the corresponding input of the control key, the previous key other outputs connected to the inputs of the next key, control key control input connected to the delay line, the outputs of control key information device are the outputs
The device diagram is shown in the drawing.

 The device for priority servicing of requests contains an n-bit register of requests 1, element OR 2, element AND 3 of the cascade consisting of the first key 4, second key 5, third key 6, ... n-th key n, control keys 7, information inputs device 8, a confirmation line for detecting a request 10, a permission line for accepting a request 11, information outputs of the device 12, a line for resetting a request from a request register 9, a delay line 13.

 The priority service device operates as follows. The individual inputs of the bits of the register of requests 1 from information inputs 8 receive requests for servicing applications, setting the corresponding bits of the register in a single state. Requests have their own priorities, strictly related to register bits. From the output of the request register 1, the request signals, each in its own communication line, goes to the inputs of the OR 2 element. If there is at least one request in the register 1, the signal from the output of the OR 2 goes to one of the inputs of the AND 3 element. When the processing device is ready, as evidenced by the presence of a signal on the permission line for accepting the request 10, from the output of the AND 3 element, the signal goes to the input of the first key 4, thereby opening it. If the detected request had the highest priority, then the corresponding signal from the output of the first key 4 goes to the information input of the control key 7. If the detected request had a lower priority, then the signals from the outputs of the first key, except the first, go to the information inputs of the second key 5, where also, 1 application is selected, and so on up to the nth key n, on which the application with the lowest priority is detected. As a result, a single code corresponding to the request with the highest priority will be generated at the information inputs of the control key 7. If there is no signal on the delay line 13, a single code is sent to the information outputs of the device 12. This code is also sent along the line of the reset request 9 to the request register 1. This signal resets the corresponding bit of the request register 1, preparing it to receive the next request of the same priority level .

 When servicing a request, there is no enable signal on the permission line for accepting request 11, so the device waits for the end of the request processing, after which the device is ready to process requests. Requests are not lost, since each request has its own category of request register 1. After processing the request, an enable signal arrives on the request line 11, and the device is ready to process the following requests.

 Thus, as a result of one cycle of the device’s operation, the request with the highest priority among the requests that have arrived at the moment will be found.

 Since in the proposed device, compared with the prototype [2], the total number of elements is reduced by about half due to the elimination of priority register registers, comparison schemes, elements of the first and second groups, as well as a clock generator, all this leads to a decrease in the intensity failures of the proposed device is approximately doubled and, consequently, to the same increase in reliability of the device. In addition, the device allows you to increase the number of inputs for requests not by cascading, but by parallel increasing the number with a minimum number of logic elements, this is ensured by the presence of a control key 7. This reduces the amount of equipment and expands the functionality of the device.

 The increase in speed is achieved by the fact that the signal generation for servicing one request is provided during the work cycle, in contrast to the prototype, there is no clock pulse generator that stops whenever a request from the application of the highest priority is detected. This improves the throughput of the device.

 In addition, during the operation cycle of the device, all incoming applications are serviced, including low priority ones.

 Thus, the goal is achieved.

Literature
1. USSR author's certificate 962948, cl. G 06 F 9/46, 1982.

 2. USSR copyright certificate 898435, cl. G 06 F 9/46, 1982 - prototype.

Claims (1)

A priority request servicing device comprising a request register, the single bit inputs of which are connected to the information inputs of the device, and the outputs are connected to the inputs of the OR element, the output of which is connected to the first input of the AND element, the second input of which is connected to the device request permission line, the key cascade inputs are connected with single outputs of the request register, the output of the AND element is connected to the first cascade key, each first cascade key output corresponding to a certain priority is connected to the control -governing input of the next stage and with the control key information input key, the other key outputs of the preceding stage are connected to the following stage key-input, the outputs of the control key device connected to data-output register, and requests the control input of a control key is connected to the delay line.