RU2319198C1 - Device for priority servicing of requests - Google Patents

Abstract

FIELD: computer engineering, possible application for designing devices for priority servicing of requests.

SUBSTANCE: device contains inverter, decoder, delay elements, request register, switches, OR element, OR-NOT element, AND element.

EFFECT: increased reliability and increased speed of device operation.

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Description

The invention relates to the field of computer technology, in particular to priority request servicing devices.

A prioritized request servicing device [1] is known, which contains a request register, the single bit inputs of which are connected to the information inputs of the device, and the outputs are connected to the inputs of the OR element, the output of which is connected to the first input of the And element, the second input of which is connected to the control input of the device, the output element And is connected to the enable input of the clock generator, the output of the generator is connected to the input of the counter.

The disadvantage of this device is the low speed, high complexity and, as a consequence, low reliability.

The purpose of the invention is to increase the reliability and speed of the device by reducing its hardware composition and improving the control circuit.

This goal is achieved by the fact that in the device of priority service of requests containing the register of requests, the unit inputs of the bits of which are connected to the information inputs of the device, and the outputs are connected to the inputs of the OR element and valve inputs, the outputs of which are connected to the device outputs and to the zero inputs of the corresponding request bits and the inputs with the corresponding outputs of the decoder, the zero output of the decoder through the delay element is connected to the first input of the decoder, the first output of the decoder through the element the delay is connected to the second input of the decoder, the second output of the decoder through the delay element is connected simultaneously with the first and second inputs of the decoder, the third output of the decoder through the delay element is connected to the third input of the decoder, the fourth output through the delay element is connected simultaneously with the third and first inputs of the decoder, the fifth output through the delay element is connected simultaneously with the third and second inputs of the decoder, the sixth output through the delay element is connected simultaneously to all inputs of the decoder, the seventh the output is connected only to the corresponding valve input, the outputs of which are connected to the inputs of the OR element, the output of which is connected to the first input of the AND element, the second input of which is connected to the outputs of the OR element, the third and fourth inputs are connected to the control inputs of the device, and the output of the AND element connected to the enable input of the decoder and the input of the inverter, the output of which is connected to all information inputs of the decoder.

The device diagram is shown in the drawing.

The priority request servicing device comprises an inverter 1, a decoder 2, delay elements 3, a request register 4, valves 5, an OR element 6, an OR-NOT element 7, an AND 8 element, an incoming request line 9, information outputs of the device 10, a signal line of the processing device about the beginning of work 11, the signal line of the processing device for permission to receive the next request 12, allowing the input of the decoder 13, the input of the inverter 14, the control line of the valves 15, the information lines of the valves 16, the line for resetting the request from the request register 17.

The priority service device operates as follows.

The inputs of the register 4 from the information inputs 9 receive requests requiring service applications. Requests set the corresponding category of the request register to a single state. Requests have their own priorities, strictly related to the bits of the query register. From the output of the register, each signal in its own line goes to the input of the OR element 6. If there is at least one request in the register, the signal from the output of the OR 6 goes to the input of the element AND 8, when the processing device is ready, as evidenced by the signals from the control inputs of the device 11 and 12, the signal from the output And 8 goes to the enable input 13 of the decoder, putting it into operation, and goes to the input of the inverter 1. The inverter generates a pulse signal corresponding to logical zero and sends it to all the information inputs of the decoder 2. Decipher the ator generates a single zero code and sends it to the control inputs of valves 15 5, thus, the zero bit of the request register 4 is interrogated. If there is no request of this priority, the signal from decoder 2 is fed back through the delay element 3 to the information inputs of decoder 2 to as an application number code in the request register 4 with a lower priority. Thus, all the bits of register 4 are alternately polled for the presence of an application of this priority.

After finding the application with the highest priority, as evidenced by the signal from the output of the valves 5, which is fed to the input of OR-NOT 7, the priority request service device through the inhibitory input 18 of the AND 8 element from the OR-NOT 7 element stops the decoder. The next request processing cycle will begin after the serving system gives a signal that opens the And 8 key on line 12, indicating that the processing device has served the previous request and is ready to accept the next one.

Thus, as a result of one cycle of the device’s operation, a request with the highest priority among the requests that have arrived at a given time will be found.

Since in this device, in comparison with the prototype, the total number of elements is reduced by about one and a half times due to the exclusion of the trigger, counter, clock generator and their control circuits, all this leads to an increase in speed, a decrease in the failure rate by about a factor of two, and therefore to an increase reliability.

Reducing energy consumption compared to the prototype is provided by the exception of a constantly running clock.

In addition, after finding the highest priority application, the device starts the cycle anew, which allows faster servicing of higher priority applications.

Literature

1. Patent for invention No. 2182354, Cl. G06F 9/18.

Claims (1)

A priority request servicing device containing a request register, the single inputs of the bits of which are connected to the information inputs of the device, and the outputs are connected to the inputs of the OR element and information inputs of keys, the outputs of which are connected to the outputs of the device and with the zero inputs of the corresponding bits of the request register, and the control inputs are corresponding outputs of the decoder, characterized in that delay elements and an inverter are introduced into it, while the zero output of the decoder through the delay element is connected n with the first input of the decoder, the first output of the decoder through the delay element is connected to the second input of the decoder, the second output of the decoder through the delay element is connected simultaneously with the first and second inputs of the decoder, the third output of the decoder through the delay element is connected to the third input of the decoder, the fourth output is through the delay element connected simultaneously with the third and first inputs of the decoder, the fifth output through the delay element is connected simultaneously with the third and second inputs of the decoder, the sixth output through the element the delay is connected simultaneously to all inputs of the decoder, the seventh output is connected only to the corresponding input of the keys, the outputs of which are connected to the inputs of the OR-NOT element, the output of which is connected to the first input of the AND element, the second input of which is connected to the output of the OR element, the third and fourth inputs are connected with the control inputs of the device to which the signals “start of work” and “permission to receive the next request” are sent, and the output of the And element is connected to the enable input of the decoder and the input of the inverter, the output of which is so me all data inputs of the decoder.