RU2251145C2 - Priority access device with limit on query search - Google Patents

Abstract

FIELD: computer science.

SUBSTANCE: device has n-byte query register, query limits location systems, each of which consists of counting timer and OR element, OR element, AND element, keys cascade.

EFFECT: higher reliability and speed of operation.

1 dwg

Description

The invention relates to the field of computer technology, in particular to priority request servicing devices. A device for priority service requests [1], containing a register of applications, the inputs of which are connected to the information inputs of the device, priority registers, AND, OR elements, a counter whose outputs are connected to the first inputs of the comparison circuits, the outputs of which are connected to the first inputs of the elements And the first groups, and the counter counter input is connected to the output of the AND element, the first inverse of which is connected to the zero input of the control trigger, whose single input is connected through the first OR element to the input control devices with a single counter input, and a pulse generator.

The disadvantage of this device is the availability of limited functionality, since with a large number of multi-priority applications, the waiting time for applications with low priority is very long, which in some cases is unacceptable and can lead to the loss of low-priority applications.

The purpose of the invention is to increase the reliability and speed of the device by reducing its hardware and improving control over its operation.

The task is achieved in that the priority service device contains a request register, the unit inputs are connected to the inputs of the OR element and the inputs of the cascade of keys. The outputs of the OR element are connected to the first input of the AND element, the output of which is connected to the controlled input of the key cascade.

The device diagram is shown in the drawing. The priority access device consists of a request register 1, an OR element 2, a first key of a cascade 3, an OR element of a request restriction system 4, a timer-counter of a request restriction system 5, a second cascade key 6, an And 7 element, an nth key of a key cascade 8 , information inputs of device 9, reset lines of requests 10, installation lines 11, permission lines for accepting requests 12, information outputs of device 13.

The device accepting the priority service request operates as follows.

The individual inputs of the bits of the register of requests 1 from information inputs 9 receive requests for servicing applications, setting the corresponding bits of register 1 in a single state. From the output of the request register 1, the request signals, each in its own communication line, go to the inputs of the OR 2 element. If there is at least one request in the register 1, the signal from the output of the OR 2 goes to the first input of the And 7 element, when the processing device is ready, about which indicates the presence of a signal on the permission line for accepting the request 12, from the output And 7 the signal goes to the control input of the first key of the cascade 3, the information inputs of this key 3 receive a signal from the inputs of the request register 1. Provided that there is an application, i.e. setting one of the bits of the register of requests 1 to a single state and the signal of permission to accept the request, there will be a single signal at the controlled input of the first key of cascade 3, which will ensure the passage of signals from the information inputs of the first key to its information outputs, if the request had the highest priority, then a single signal will pass along the line connecting the 1st output of key 3 with the information output of the device and the controlled input of the second key of cascade 6, thereby closing it, if the request had a lower priority, then at the first exit 13 th device output information will be a senior. Thus, the cascade of keys, in which each subsequent key is less than the previous key, the controlled input of the subsequent key is connected to the output of the senior bit of the previous key, selects a unit code corresponding to the request that is generated at the information outputs of the device 13, the generated unit code is also sent to the reset line requests 10, setting to zero the corresponding bit of the register of requests 1, thereby preparing it for receiving the next request with the same priority. In addition, with the help of the system for restricting the location of requests, it is possible to limit the location of the request in the system, i.e. if within a certain time from the moment of receipt of the request to the priority access device it will not be served, then this type of request will be reset. The request finding restriction system consists of a timer counter 5, the signal input of which is connected to the corresponding output of the request register 1, the control inputs are connected to the installation lines 11, and the output is connected to the OR element 4, which is located on the line of the request reset of the corresponding request, i.e. . one input of the OR element 4 is connected to the output of the cascade of keys along the corresponding reset line of the request, and the second input is connected to the output of the timer-counter 5, the signal from the output of OR 4 resets the corresponding bit of the request register 1. The operation of the system for restricting the location of requests is that after after the request signal has set the corresponding bit of the request register 1 to a single state, the single signal from the corresponding output of the request register 1 is fed to the signal input of the timer counter 5, in turn, the timer counter 5, which th can be set to a different waiting time for request service along the installation lines 11, starts to decrease the value until it is reset to zero, if the timer counter 5 is reset before the request is served, a single signal from the output of the timer counter 5 will go to one of the inputs of the element OR 4, a single signal appears at its output, which resets the corresponding bit of the request register to zero, if the request is served before the timer counter 5 is reset, the signals on the installation lines 11 will set the timer counter 5 to the original state. The system for restricting existing requests can be installed on one of the requests, or on several or all, i.e. Each request will have its own system for limiting the location of the request.

Thus, as a result of one cycle of the device’s operation, a request with the highest priority of the time that has arrived at the given time will be found, and the request will also be reset with a service time limit if it has not been serviced for a specified time.

In addition, during the operation cycle of the device, all incoming applications are serviced, including low priority ones.

Thus, the goal is achieved.

LITERATURE:

1. USSR Copyright Certificate No. 962948, Cl. G 06 F 9/46, 1982.

Claims (1)

A priority access device with a restriction on finding an application, containing a p-bit register of requests, the single bit inputs of which are connected to the information inputs of the device, and the outputs are connected with the corresponding systems for restricting the location of requests, each of which consists of a timer counter and an OR element, a signal input of a timer counter of the corresponding request restriction system is connected to the corresponding output of the query register, the control input of the timer counter is connected to the installation line, and the output to is single with the input of the OR element of this query restriction system, the second input of which is connected to the corresponding query reset line, the output signal of the OR element of the query restriction system resets the corresponding bit of the query register, also the outputs of the query register are connected to the OR element, the output of which is connected to the first input of the element And, the second input of which is connected to the permission line for accepting the request, and the output is connected to the controlled input of the first key of the cascade of keys, whose information inputs are connected to by the outputs of the request register, the cascade of keys consists of n-keys, with each next key being one bit less than the previous one, the output of the highest bit of the previous key is connected to the controlled input of the subsequent key and the information output of the device, the rest of the information outputs of the key are connected to the information inputs of the subsequent key, except of the nth, the nth key output is connected to the information output of the device, the information outputs of the device are connected to the request reset lines.