RU2216768C2 - Priority request servicing device - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: priority request servicing device noted for reduced hardware requirements and improved control of its operation has request register, OR gate, AND gate, clock generator, counter, switches, register, demultiplexer, and decoder. EFFECT: enhanced reliability and speed of device. 1 cl, 1 dwg

Description

 The invention relates to computer technology, in particular to priority request servicing devices.

 A device for priority servicing of requests [1], comprising a register of applications, the inputs of which are connected to the information inputs of the device, priority registers, AND, OR elements, a counter whose outputs are connected to the first inputs of the comparison circuits, the outputs of which are connected to the first inputs of the elements AND the first groups, and the counter counter input is connected to the output of the AND element, the first inverse of which is connected to the zero input of the control trigger, the single input of which is connected through the first OR element to the input control devices with a single counter input, and a pulse generator.

 The disadvantage of this device is the availability of limited functionality, since with a large number of different-priority applications, the waiting time for applications with a low priority is very long, which in some cases is unacceptable and can lead to the loss of low-priority applications.

 The closest technical solution to the proposed one is a device for servicing queries [2], which allows to expand the functionality of the device by providing accounting for latency when servicing queries and containing a register of applications, priority registers made in the form of summing counters, two groups of elements AND, two groups elements OR, counter, pulse generator and frequency divider.

 The disadvantage of this device is the low speed, high complexity and, as a consequence, low reliability.

 The purpose of the invention is to increase the reliability and speed of the device by reducing its hardware and improving control over its operation.

 This goal is achieved by the fact that in the device priority service requests, containing a register of requests, the unit inputs of the bits of which are connected to the information inputs of the device, and the outputs are connected to the inputs of the OR element, the output of which is connected to the first input of the element And, the second input of which is connected to the permission line accepting the request, and the output of the And element is connected through a key to the enable input of the clock generator, the output of the generator is connected through the key to the counter input. Information outputs of the counter are connected through the register and key to the control of the demultiplexer and to the inputs of the decoder, the outputs of which are sent to the information outputs of the device.

 The device diagram is shown in the drawing.

 The priority request servicing device comprises a request register 1, an OR element 2, an AND element 6, a clock pulse generator 10, a counter 5, a key controlling the input of the counter 8, a key controlling the input of the register 3, a register 4, a demultiplexer 7, a key controlling the input of the decoder 9, the decoder 11, the information inputs of the device 12, the line for the acceptance of the request 13, the line for confirming the detection of the request 14, the information outputs of the device 15, the line for resetting the request from the request register 16.

 The priority service device operates as follows. The individual inputs of the bits of the register of requests 1 from information inputs 12 receive requests for servicing applications, setting the corresponding bits of the register in a single state. Requests have their own priorities, strictly related to register bits. From the output of the request register 1, the request signals, each in its own communication line, goes to the inputs of the OR 2 element. If there is at least one request in the register 1, the signal from the output of the OR 2 goes to one of the inputs of the And 6 element, when the processing device is ready, as evidenced by the presence of a signal on the permission line for accepting the request 13, from the output of the And 6 element, the signal goes to the input of the counter 5, setting it to the initial state, and to the key 8. The signals from the output of the clock pulse generator 10 go to the counting input of the binary counter 5, which starts to work and form at its outputs a sequence of binary codes corresponding to the priority numbers of the applications received.

 Binary codes from the output of counter 5 go to register 4, from the outputs of register 4 the binary code goes to the control inputs of the demultiplexer 7, information is searched on the information inputs of the demultiplexer, which are connected to the outputs of the request register 1. Each signal at the information input of the demultiplexer 7 corresponds to a discharge in the request register 1. Counter 5, with each cycle of operation, forms a binary sequence of priority numbers of applications, starting with the highest priority, until the two matches The priority code number generated by the counter and the priority number of the request requiring service. That is, if there is no service request for the i-th application, then the corresponding bit of the request register 1 remains in the zero state, as a result, the signal at the output of the demultiplexer 7 will also be zero, then key 3 will remain open and register 4 will accept the following binary code, the device proceeds to check the application with a lower priority.

 After the discovery of the application with the highest priority, i.e. after the binary code coincides with the i-th digit of the request register 1, the key 3 is closed and the binary code of the detected application with the highest priority is stored on register 4. The counter continues to generate binary codes until it generates all possible codes, after which a signal passes through the request detection line 14, which opens the key 9, after which the binary code of the selected request stored in register 4 is transmitted to the decoder 11, on it a single code is generated, which arrives at the information outputs of the device 15. A signal on the request detection line 14 says that the device has detected a request with the highest priority and a single code is set at the information outputs of the device. A single code, in addition to confirming the detected request, is sent along the line for resetting the request 16 to the request register 1. This signal resets the corresponding bit of the request register 1, preparing it to receive the next request of the same priority level.

 When servicing a request, there is no permission signal on the request acceptance permission line 13, so the device waits for the end of the request processing, after which the device is ready to process requests. Requests are not lost, because each request has its own category of request register 1. After processing the request, the enable signal 13 arrives at the request line, which indicates that the device can process the following requests.

 Thus, as a result of one cycle of the device’s operation, a request with the highest priority among the requests that have arrived at a given time will be found.

 Since in the proposed device, in comparison with the prototype [2], the total number of elements is approximately halved due to the elimination of priority register registers, comparison schemes, elements of the first and second groups, as well as controls for starting and stopping the clock generator, that’s all this leads to a decrease in the failure rate of the proposed device by about half and, therefore, to increase the reliability of the device.

 The increase in speed is ensured by the fact that, firstly, the formation of a signal for servicing one request is provided during the device’s operation cycle without stopping the clock generator, in contrast to the prototype, where the clock generator stops whenever a request from the highest priority request is detected. This improves the throughput of the device.

 In addition, during the operation cycle of the device, all incoming applications, including low priority ones, are serviced.

 Thus, the goal is achieved.

Sources of information
1. USSR author's certificate 962948, cl. G 06 F 9/46, 1982.

 2. USSR copyright certificate 898435, cl. G 06 F 9 46, 1982 - prototype.

Claims (1)

 A priority request servicing device containing a request register, the single bit inputs of which are connected to the information inputs of the device, and the outputs are connected to the inputs of the OR element, the output of which is connected to the first input of the AND element, the second input of which is connected to the permission line of the device request, the output of the And element is connected with the counter input and a key, the output of the clock generator is connected to the counter input via a key, characterized in that it also includes a decoder, a key that controls the input for the encoder, demultiplexer, register, key that controls the input of the register, while the outputs of the decoder are connected to the information outputs of the device, also the code from the outputs of the device is fed through the reset line of the request to the request register, the control inputs of the demultiplexer are connected to the outputs of the register, each signal at the information input of the demultiplexer corresponds to the category in the request register, the key that controls the input of the decoder is designed to pass the code stored in the register to the decoder when it arrives at this key h signal line confirmation of detection supplied from the counter, the output of the demultiplexer controls a key input of the control register, the key for transmission of the binary code from the counter to the register.