RU2209509C2 - Orthogonal-signal biplane coder - Google Patents

Abstract

FIELD: automation and computer engineering; radio communication systems using noise-like signals. SUBSTANCE: device has input register, bit-to-bit modulo two adding unit with two m-digit inputs, m EXCLUSIVE OR gates, pairwise conjunction unit for odd and even digits with one m-digit input, m/2 AND gates, modulo two adder, sign inversion unit, clock generator, and binary counter with even number of bits. EFFECT: simplified design of device. 1 cl, 4 dwg, 1 tbl

Description

 The invention relates to automation and computer engineering and can be used in radio engineering communication systems with noise-like signals using digital methods of forming large systems of complex orthogonal signals (see [1], pp. 101-102).

где m - число разрядов двоичного счетчика;
v_i∈{0,1} - выход i-го разряда двоичного счетчика;
u_i∈{ 0,1} - двоичные входы устройства, определяющие номер ортогональной кодовой последовательности;
u₀∈{ 0,1} - вход инверсии (дополнения по модулю два) системы ортогональных кодовых последовательностей.A number of devices are known that can be used to form orthogonal signal systems. For example, to form the systems of orthogonal Walsh signals, an encoder for the first-order Reed-Muller code R (1, m) (see [2], p. 406, Fig. 14.8) based on Sylvester-type Hadamard matrices (see [ 2], p. 52-53). The symbols of the binary code sequence x _j ∈ {0,1}, j∈ {0,1, ..., 2 ^m-1 } (see [2], p. 400, formula 14.7) are mathematically described in binary arithmetic operations

where m is the number of bits of the binary counter;
v _i ∈ {0,1} - output of the i-th digit of the binary counter;
u _i ∈ {0,1} - binary inputs of the device that determine the number of the orthogonal code sequence;
u ₀ ∈ {0,1} is the inversion input (modulo two additions) of the system of orthogonal code sequences.

The first-order Reed-Muller code R (1, m) consists of a unit weight of 2 ^m (consisting of one unit "11 ... 1"), a zero weight of 0 (consisting of one zero "00 ... 0") and 2 ^{m + 1} - 2 code sequences weighing 2 ^m-1 .

A disadvantage of the known encoder R (1, m) is that the code sequences belonging to the same orthogonal system or to the opposite system have the same weight of 2 ^m-1 .

Ортогональный код одной плоскости Камерона состоит из 2^m кодовых последовательностей весом 2^m-1-2^(m-2)/2, а второй инверсной плоскости состоит из 2^m кодовых последовательностей весом 2^m-1+2^(m-2)/2.As a rule, for even m, the systems of orthogonal signals of the Cameron biplane (see [2], p. 414, Corollary II, formula 14.29, exercise 16.c) were constructed according to the formula

The orthogonal code of one Cameron plane consists of 2 ^m code sequences weighing 2 ^m-1 -2 ^{(m-2) / 2} , and the second inverse plane consists of 2 ^m code sequences weighing 2 ^m-1 +2 ^{(m-2) / 2} .

 The disadvantage of the well-known formula (2) for constructing an orthogonal biplane is complexity, since it requires m + m / 2-1 two-input logic elements EXCLUSIVE OR (adders modulo two) and m + m / 2 logic elements I. It is advisable to reduce the excess m logical elements AND.

 Closest to the proposed device is an encoding device [3], containing an information register, a control register, the first and second memory blocks, an adder block, the inputs of the information register being the information inputs of the device, the outputs of the information register are connected to the inputs of the adders block and the inputs of the second block memory and are the information output of the device, the outputs of the adder block are connected to the first inputs of the control register and the inputs of the first memory block, the outputs of the first and watts The memory blocks are connected to the second inputs of the control register, the outputs of the control register are the outputs of the control features of the device.

 A disadvantage of the known encoding device [3] is the complexity.

 The task at hand is to simplify the device.

The problem is achieved by the fact that in the device containing the input register, an additional block of bitwise addition modulo two with two m-bit inputs of m logic elements EXCLUSIVE OR, a pairwise conjunction block of odd and honest bits with one m-bit input from m / 2 logical elements And, an adder modulo two, a sign inversion unit, a clock generator, a binary counter with an even number of bits, the m-bit information input of the input register being the input of the encoder signal number, and the information The single-bit input register input is the inverse of the polar-manipulated signals to the opposite encoder value, the m-bit input register output and the binary counter information output are bitwise connected to the inputs of the first and second terms of the bitwise addition block modulo two, and the binary counter overflow output is connected with the control input of the input register entry, the m-bit output of the sum of the block of bitwise addition modulo two is bitwise connected to the input of the block in pairs conjunctions of odd and even digits, m / 2-bit output of the block of pairwise conjunction of odd and even digits is connected to the m / 2-bit input of the adder modulo two, the output of which is connected to the information input of the sign inversion unit, the counting input of the binary counter is connected to the clock output generator, a single-bit output of the input register is connected to the control input of the sign inversion block, the output of the sign inversion block is the output of the encoder. The advantage of the proposed device compared with the prototype [3] is to simplify and eliminate complex and redundant elements. Compared with the well-known rule (2) for constructing orthogonal signals of the Cameron biplane, the proposed device uses m fewer logical elements I. Compared with the well-known description of the first-order Reed-Muller codes [2] in the proposed device, the binary code sequences have their own distinctive weight of plane 2 ^m-1 ± 2 ^{(m-2) / 2} instead of a single weight of 2 ^m-1 . In addition, the proposed device allows to practically realize the formation of large systems of complex signals with the number of pulses 10 ³ ... 10 ⁶ , since the device does not have a memory unit for storing code sequences. Thus, the proposed device is significantly different from the known [1-3].

 Functional diagram of the encoder biplane of orthogonal signals is presented in figure 1, figure 2 is a timing diagram of the operation of the device, figure 3 is a view of the generated signals. The operation of the generator is characterized by a table.

 The orthogonal signal biplane encoder contains (see FIG. 1) a (m + 1) -bit input register 1, a sign inversion unit 2, a binary counter 3, a clock 4, a bitwise addition module 5 modulo two with two m-bit inputs from m logic elements EXCLUSIVE OR, block 6 pairwise conjunction of odd and even bits with one m-bit input from m / 2 logical elements And, adder 7 modulo two with m / 2 inputs, and the single-bit and m-bit information inputs of the input register 1 are respectively the input Y0 inversion of polar pulsed signals to the opposite value of the encoder and the encoder signal number input Y1, the single-bit output of the input register 1 is connected to the control input of the sign inversion unit 2, the counting input of the binary counter 3 is connected to the output of the clock generator 4, the overflow output of the binary counter 3 is connected to the control input of the input recording register 1, the m-bit output of the input register 1 and the information output of the binary counter 3 are bitwise connected, respectively, to the inputs of the first and second terms of the bitwise unit 5 modulo two, the m-bit output of the sum of block 5 of bitwise addition modulo two is bitwise connected to the input of block 6 of the pairwise conjunction of odd and even bits, the m / 2-bit output of block 6 of the pairwise conjunction of odd and even bits is connected to the inputs of the adder 7 module two, the output of adder 7 modulo two is connected to the information input of the sign inversion unit 2, the output of the sign inversion unit 2 is the output of the encoder.

The input register 1 is designed to receive and store digital codes of a composite number (Y0, Y1) for the entire period of time the formation of a complex signal:
- the code Y0∈ {0,1} determines the type of the polar-manipulated signal in the direct or inverse (opposite) code;
- the code Y1∈ {0,1, ..., 2 ^m -1} sets the binary code number of the orthogonal signal.

 Reception of the binary code from the input bus of the device is carried out under the influence of the logic level “1”, which is input to the control (synchronizing) input of the input register 1. The information on the output data bus of the input register 1 is changed by the negative edge at the write control input, that is, at the beginning of each period. If there is a logical level entry "0" at the control input, the input register 1 stores the received information for the entire time T of generating a complex signal.

 Block 2 of the sign inversion allows you to get the output signal in direct or inverse (opposite) code depending on the control logic level at the single-bit output of the input register 1. In addition, in the function of block 2 of the sign inversion, the transition from logical levels "1", "0" to analog values "+1", "-1".

The binary counter 3, counting the pulses from the clock 4, sets the period T = 2 ^m T _and biorthogonal signals. At the end of each period, according to the logical state "11 ... 1" of binary counter 3, a logical level "1" is generated at the output of overflow (zeroing) of binary counter 3. This signal controls the reception of input information in input register 1, and recording is performed at the beginning of each period.

(3)
Таким образом, в течение периода Т в зависимости от значения "0" или "1" i-го разряда m-разрядного выхода входного регистра 1 на выход i-го разряда блока 5 поразрядного сложения по модулю два поступает сигнал типа "меандр" с i-го разряда двоичного счетчика 3 в прямом или противоположном коде соответственно.Block 2 of bitwise addition modulo two with two m-bit inputs consists of m logic elements EXCLUSIVE OR. For each i-th bit from the current states v _{i of the} binary counter 3 and constant (during the period T) bias u _i specified from the m-bit output of input register 1, the bitwise addition unit 5 modulo two calculates the bitwise sum
w _i = u _i + v _i (mod 2),

(3)
Thus, during the period T, depending on the value “0” or “1” of the i-th bit of the m-bit output of the input register 1, a signal of the meander type with i -th digit of the binary counter 3 in direct or opposite code, respectively.

(4)
Сумматор 7 по модулю два с m/2 входами вычисляет значение логической операции

Таким образом, блок 6 попарной конъюнкции нечетных и четных разрядов и сумматор 7 по модулю два (см. [2], с. 414, следствие II, формула 14.29) вычисляют значение максимально-нелинейной "бент"-функции
f_j=w₁w₂+w₃w₄+...+w_m-1w_m(mod 2) (6)
Кодер биплоскости ортогональных сигналов работает следующим образом.Block 6 of the pairwise conjunction of odd and even bits with one m-bit input and with m / 2-bit output consists of m / 2 logic elements I. For each n-th output bit, the values of odd w _2n-1 and even w _2n input digits block 6 pairwise conjunction odd and even digits calculates the Boolean operation conjunction
g _n = w _2n-1 • w _2n ,

(4)
The adder 7 modulo two with m / 2 inputs calculates the value of the logical operation

Thus, the block 6 of the pairwise conjunction of the odd and even digits and the adder 7 modulo two (see [2], p. 414, Corollary II, formula 14.29) calculate the value of the maximally non-linear “bent” function
f _j = w ₁ w ₂ + w ₃ w ₄ + ... + w _m-1 w _m (mod 2) (6)
The encoder biplane orthogonal signals works as follows.

 When the power source is turned on (not shown in Fig. 1), a pulse is applied to set the binary counter 3 to the logical state "11 ... 1" and to set the push-pull D-flip-flops of input register 1 to the single state, therefore, from a single-bit output of input register 1 logic level "1" is fed to the control input of the sign inversion block 2. From the output of the overflow of the binary counter 3, the logic level "1" is supplied to the control input of the input register 1, transferring it to the reception mode of the (m + 1) -bit digital code of the composite signal number. From the m-bit output of block 5 of bitwise addition modulo two signals of the logic level “0” are supplied to the inputs of block 6 of the pairwise conjunction of odd and even digits. From the output of block 6 of the pairwise conjunction of odd and even digits, the logic level signals “0” are fed to the inputs of the adder 7 modulo two. From the output of the adder 7 modulo two signal, the logic level "0" is fed to the information input of the sign inversion unit 2, therefore, at the device output, a positive unit potential of "+1" is set.

При переходе двоичного счетчика 3 в состояние Т логический уровень "1" с выхода переполнения двоичного счетчика 3 поступает на управляющий вход записи входного регистра 1. Входной регистр 1 переходит в режим приема нового (m+1)-разрядного двоичного кода - номера биортогонального сигнала. Под воздействием следующих синхроимпульсов цикл работы устройства повторяется.The clock generator 4 generates pulses with a repetition period T _and , which are supplied to the counting input of the binary counter 3. At the end of the first clock pulse, the binary counter 3 from the state "11 ... 1" goes to the zero state, while the logic level is "0" with the output of zeroing the binary counter 3 is fed to the control input of the input register 1, translating it into the storage mode of the input code of the composite number (Y0, Y1) for the entire time T = 2 ^m T _{and the} formation of a complex signal. The logic level "0" or "1" in accordance with the input code Y0 from the single-bit output of the input register 1 is fed to the control input of the sign inversion unit 2 to form the polar-manipulated signal of the orthogonal system (plane) in the direct or inverse (opposite) code. From the m-bit output of the input register 1, the binary code Y1∈ {0,1, ..., 2 ^m -1} of the number of the orthogonal signal in the system (plane) is supplied to the input of the first term of the bitwise addition block 5 modulo two. Under the influence of each clock pulse, the binary counter 3 from the previous state goes into the next. The current state of the bits v _{i of the} binary counter 3 is fed to the input of the second term of block 5 of the bitwise addition modulo two. From the output of block 5 of bitwise addition modulo two, the calculated bitwise sum (3) is fed to the input of block 6 of the pairwise conjunction of odd and even digits. For each n-th bit of the m / 2-bit output of block 6 of the pairwise conjunction of odd and even bits, the logical operation conjunction (4) is calculated. At the output of the adder 7 modulo two, the sum (5) is calculated. At the output of the encoder, the code sequence of the orthogonal signal is described by the expression

When the binary counter 3 enters the state T, the logic level "1" from the overflow output of the binary counter 3 goes to the control input of the input register 1. The input register 1 goes into the mode of receiving a new (m + 1) -bit binary code - biorthogonal signal number. Under the influence of the following clock pulses, the cycle of the device is repeated.

 On the time diagrams of the operation of the device (Fig. 2), it is shown that the binary counter 3 (diagrams from the top 12-15) performs the division of the repetition rate of clock pulses arriving at its counter input from the output of the clock generator 4 (diagram 11). If counter 3 goes into state T, then its overflow output sets logic level “1” (diagram 16) and register 1 receives from the input data bus of the device digital double codes Y0, Y1 (diagrams 1-5). At the end of the next clock pulse, counter 3 goes to zero, at its overflow output the logic level is set to “0” and register 1 goes into the storage mode of input codes Y0, Y1 for the whole time T of the formation of a complex signal (diagrams 6-10). During time T, new digital codes Y0, Y1 (diagrams 1-5) are prepared at the inputs of register 1. Depending on the signals at the corresponding outputs of block 5 (diagrams 7-20), signals are generated at the outputs of block 6 (diagrams 21, 22). Depending on the output signal of the adder 7 (diagram 23) and on the output signal of the single-bit output of register 1 (diagram 6), the output polar-manipulated signal of the device (diagram 24) is generated in direct or opposite code.

 The table shows the code sequences of biorthogonal signals generated by the proposed device with a five-bit input data bus of register 1 (m = 4), where the symbols "+" and "-" denote pulses of unit amplitude of positive and negative polarity, respectively. Depending on the five bits of the input code (Y0, Y1) (in the column table from the 2nd to the 6th), 1 of 32 sixteen-pulse polar-manipulated signals is generated (in the column table from the 7th to the 22nd).

Вторые шестнадцать сигналов (фиг. 3 (Б), строки 17-32 таблицы) также образуют ортогональную систему сигналов, так как

Сигналы φ_i(t) и ψ_i(t) противоположны,

Преимущество предлагаемого устройства по сравнению с аналогом и прототипом заключается в упрощении и исключении сложных и избыточных элементов. По сравнению с известным правилом (2) построения ортогональных сигналов биплоскости Камерона предлагаемое устройство использует на m меньше логических элементов И. По сравнению с прототипом в предлагаемом устройстве исключен блок памяти, а сумматор по модулю (Т-1) заменен на более простой в техническом исполнении блок 5 поразрядного суммирования по модулю два. По сравнению с известным описанием кодов Рида-Маллера первого порядка [2, 3, 4] в предлагаемом устройстве двоичные кодовые последовательности имеют свой собственный отличительный вес плоскости 2^m-1±2^(m-2)/2 вместо одного веса 2^m-1. Кроме того, предлагаемое устройство позволяет практически реализовать формирование больших систем сложных сигналов с числом импульсов 10³...10⁶, так как в устройстве отсутствует блок памяти для хранения кодовых последовательностей.The first sixteen signals (Fig. 3 (A), rows 1-16 of the table) form an orthogonal system, since

The second sixteen signals (Fig. 3 (B), rows 17-32 of the table) also form an orthogonal signal system, since

The signals φ _i (t) and ψ _i (t) are opposite,

The advantage of the proposed device in comparison with the analogue and prototype is to simplify and eliminate complex and redundant elements. Compared with the well-known rule (2) for constructing orthogonal signals of the Cameron biplane, the proposed device uses m less logical elements I. Compared with the prototype, the proposed device excludes a memory block, and the adder modulo (T-1) is replaced by a simpler one in technical design block 5 bitwise summation modulo two. Compared with the well-known description of the first-order Reed-Muller codes [2, 3, 4] in the proposed device, the binary code sequences have their own distinctive weight of the plane 2 ^m-1 ± 2 ^{(m-2) / 2} instead of one weight 2 ^m-1 . In addition, the proposed device allows to practically realize the formation of large systems of complex signals with the number of pulses 10 ³ ... 10 ⁶ , since the device does not have a memory unit for storing code sequences.

Sources of information
1. Varakin L.E. Communication systems with noise-like signals. - M .: Radio and communications, 1985 .-- 383 p.

 2. Mc-Williams F.J., Sloan N.J.A. Theory of error correction codes. - M.: Communication, 1979. - 744 p.

 3. Grinenko N. I., Lysakovsky A. F., Shevchuk P. S. Orthogonal-opposite signal generator / Copyright certificate of the USSR 1697071 A1, cl. MKI G 06 F 1/02.

 4. Hall M. Combinatorics. - M.: Mir, 1970 .-- 424 p.

Claims (1)

 An orthogonal signal biplane encoder containing an input register, characterized in that an additional two-bit modulus addition module with two m-bit inputs of m logic elements EXCLUSIVE OR, an odd and even bit pair conjunction block with one m-bit input of m / 2 logical elements And, an adder modulo two, a sign inversion unit, a clock generator, a binary counter with an even number of bits, the m-bit information input of the input register being the input of the encoder signal number, and The single-bit formation input of the input register is the inverse of the polar-manipulated signals to the opposite value of the encoder, the m-bit output of the input register and the information output of the binary counter are bitwise connected to the inputs of the first and second terms of the bitwise addition block modulo two, and the binary counter overflow output is connected with the control input of the input register entry, the m-bit output of the sum of a block of bitwise addition modulo two is bitwise connected to the input of the block pairwise conjunction of odd and even bits, m / 2-bit output of the block of pairwise conjunction of odd and even bits is connected to the m / 2-bit input of the adder modulo two, the output of which is connected to the information input of the sign inversion unit, the counting input of the binary counter is connected to the output a clock generator, a one-bit output of the input register is connected to the control input of the sign inversion block, the output of the sign inversion block is the output of the encoder.

Images