RU2150785C1 - Adaptive system for transmission and reception of digital information - Google Patents

Abstract

FIELD: communication equipment, computer engineering. SUBSTANCE: transmitting part of device has buffer register. Receiving part of device has modulo two adder, shift register, AND gate and control unit, which has first and second buffer registers, clock oscillator, and delay gate. Goal of invention is achieved by introduced encoder and decoder for information to be transmitted with respective processors, two additional shift registers, second delay gate, as well additional modulo two adder. EFFECT: increased reliability of digital information transmission through direct channel due to detection of decoding errors by receiver. 2 dwg

Description

 The invention relates to computer and communication technology and can be used to build local networks, providing the ability to transmit and receive discrete information.

 A known system for transmitting and receiving discrete information, containing on the transmitting side an information channel from a series-connected subtracting counter, decoder, inverter, coincidence unit, shift register and delay element, and on the receiving side is a series-connected pseudo-random sequence allocation unit, an adder modulo two and an inverter associated with a counter for selecting channels, in each of which a pseudo-random sequence generator is installed, a comparison unit summing the counter and a drive (see., e.g., the description to author's certificate USSR N 886296, cl. H 03 M 7/04, 1980).

 The disadvantage of such a system is its complexity, which leads to a relatively low reliability in operation and low reliability of information transfer.

 Known adaptive system for receiving discrete information encoded by a correction code, having a drive with a memory unit, registers, a block of keys and adders (see, for example, the description of the invention to the USSR copyright certificate N 1674384, class H 03 M 13/00, 1988) .

 The disadvantages of the system are its implementation complexity, as well as the need to correct the code combination by transferring it to the drive and correcting erroneous bits.

 The closest known for its technical essence and the achieved result is an adaptive system selected for prototype transmission and reception of discrete information, containing on the transmitting side an information channel including a buffer register attached to the communication line, on the receiving side - an adder modulo two, whose first input is connected via a shift register to the communication line, AND elements and a control unit having first and second buffer registers, a clock generator and a delay element LCDs (see, for example, the description of the invention to the USSR copyright certificate N 1691965, class H 03 M 13/00, 1989).

 The disadvantages of the system include the transmission of the response error vector over the communication line in the opposite direction.

 The essence of the claimed invention is expressed in the aggregate of essential features sufficient to achieve the technical result provided by the invention, which is expressed in increasing the reliability of transmitting digital information on a direct channel for transmitting digital information by detecting decoding errors at the receiving side of the system.

 The claimed combination of essential features is in direct causal relationship to the achieved result.

 The novelty of the proposed system is that it additionally introduces an encoder and decoder of transmitted information with the corresponding first and second processors, two additional shift registers and a second delay element, as well as an additional adder modulo two, with the first buffer register, encoder and first processor connected in series, forming a direct channel for transmitting discrete information, the second buffer register, decoder and second processor are connected in series, forming a reverse channel for transmitting disk information, the second buffer register through additional shift registers is connected respectively with the first and second adders modulo two, connected through the first and second elements And, the last of which is connected through the first processor to the first buffer register of the forward transmission channel discrete information, while the shift register is connected to an additional adder modulo two, and the clock generator through the delay element is connected but to the second element And, it additionally introduces an encoder and decoder of the transmitted information with the corresponding first and second processors, two additional shift registers and a second delay element, as well as an additional adder modulo two, with the first buffer register, encoder and first processor connected in series forming a direct channel for transmitting discrete information, the second buffer register, decoder and second processor are connected in series, forming a reverse channel for transmitting discrete information, the second buffer the register through additional shift registers is connected respectively with the first and second adders modulo two, connected through the first and second elements And, the last of which is connected through the first processor to the first buffer register of the direct channel for transmitting discrete information, introduced into the reverse channel for transmitting discrete information this shift register is connected to an additional adder modulo two, and the clock generator through a delay element is connected to the second element I.

 Comparison of the claimed technical solution with the prototype made it possible to establish compliance with its criterion of "novelty", since it is not known from the prior art.

 The proposed system is industrially applicable by existing means and meets the criterion of "inventive step", since it does not explicitly follow from the prior art, while the latter does not reveal any transformations characterized by significant features distinguishing from the prototype to achieve the indicated technical result.

 Thus, the proposed technical solution meets the established conditions of patentability of the invention.

 The other known technical solutions for a similar purpose with similar significant features by the applicant was not found.

 In FIG. 1 shows a structural electrical diagram of the proposed system, in FIG. 2 - time diagrams of the system.

 The adaptive system for transmitting and receiving discrete information contains on the transmitting side a first buffer register 1, encoder 2, a first processor 3, a direct channel 4 for transmitting discrete digital information, on the receiving side a second buffer register 5, decoder 6, second processor 7, shift register 8 , buffer register 9, additional shift registers 10 and 11, adders modulo two 12 and 13, the first element And 14, the return channel 15 for transmitting digital information, the second element And 16, the delay element 17, the clock generator 18.

 The proposed system works as follows.

(каждый разряд которого является "0" или "1"). K - разрядное сообщение A_j кодируется системой кодирования CK_i;,

, (n≠N) в m-разрядный кодовый вектор (где k - информационные разряды, a m-k избыточные разряды, вводимые в k - разрядное сообщение A_j с целью повышения достоверности передаваемой информации). Алгоритм кодирования системы кодирования CK_i, работает таким образом, что всего кодером 2 (который реализует алгоритм кодирования CK_i) может быть сгенерировано n m-разрядных кодовых векторов (X₁, X₂,...X_n), для каждого из которых справедливо условие

(где X_i произвольный i-й кодовый вектор из множества кодовых векторов, входящих в CK_i). Количество m-разрядных кодовых векторов (n), генерируемых кодером 2, реализующих алгоритм кодирования CK_i, меньше общего количества m-разрядных кодовых векторов, и справедливо условие n < 2^m.By a command from a control device (not shown) on the input side, a control signal is received at the input of the first buffer register 1, under the influence of which discrete (binary) information in the form of a k - bit message A _{j is} received from the first buffer register 1 at the input of encoder 2,

(each digit of which is "0" or "1"). K - bit message A _j is encoded by the coding system CK _i ;,

, (n ≠ N) to the m-bit code vector (where k are information bits, and mk are the excess bits introduced into the k-bit message A _j in order to increase the reliability of the transmitted information). The coding algorithm of the coding system CK _i , works in such a way that, in total, n m-bit code vectors (X ₁ , X ₂ , ... X _n ) can be generated by encoder 2 (which implements the coding algorithm CK _i ), for each of which fair condition

(where X _{i is} an arbitrary ith code vector from the set of code vectors included in CK _i ). The number of m-bit code vectors (n) generated by encoder 2 implementing the encoding algorithm CK _i is less than the total number of m-bit code vectors, and the condition n <2 ^{m is} valid.

, который поступает на вход 1 первого процессора 3, в котором запоминается. C выхода 1 первого процессора 3 кодовый вектор X_i поступает на вход прямого канала 4 передачи цифровой информации.As a result of the operation of encoder 2, the k-bit message A _j is encoded into one of the m-bit code vectors

, which is input 1 of the first processor 3, which is stored. From the output 1 of the first processor 3, the code vector X _i is input to the direct channel 4 for transmitting digital information.

.In channel 4, the code vector X _{i is} affected by interference (F), which can introduce errors (under the influence of interference F in any of the m-bits of the code vector X _i , the contents of the binary bit can be replaced by the opposite value, for example, 0 ---> 1, 1 ---> 0), as a result of which the code vector X _{i is} transformed into the code vector X _i

.

On the receiving side of the system, from the output of channel 4, the code vector X ' _i is input to the second buffer register 5, from the output of which the code vector X' _{i is} fed to the input of decoder 6, where it (code vector X ' _i ) is decoded into code vector Y _i .

- состояние "правильное декодирование";
X_i ≠ Y_i,

- состояние "ошибка декодирования";
X_i ≠ Y_i,

- состояние "отказ от декодирования".As a result of the operation of decoder 6, the code vector X ' _i is converted to the code vector Y _i (X' _i ---> Y _i ), and three states are possible:
X _i = Y _i ,

- state "correct decoding";
X _i ≠ Y _i ,

- state "decoding error";
X _i ≠ Y _i ,

- state "reject decoding".

.On the receiving side of the state system: “correct decoding” and “decoding error” are not distinguishable. The "decoding error" state at the receiving side of the system is not detected (any CK _i has a certain probability of decoding error

.

The code vector Y _i from the output of decoder 6 is input 1 of the second processor 7. From the output 1 of the second processor 7, the code vector Y _i is input to the m-bit shift register.

By a command from a control device (not shown) at the receiving side from the buffer register 9, the input code m X ₁ , X ₂ , ... X _n (the number of m-bit shift registers 10) are input to the inputs of m-bit additional shift registers 10 and 11 , ... 11 is equal to the number of code vectors (n) of the coding system CK _i ). The reference code vectors X ₁ , X ₂ , ... X _n (coding systems CK _i ) from the outputs of the m-bit shift registers 10 and 11 are fed to one of the inputs of the m-bit adders in the module two 12 and 13, respectively (number m -digit adders modulo two (12, ... 13) is equal to the number of m-bit shift registers (10, ... 11) and equal to the number of code vectors n). At the other input of the m-bit adders modulo two 12 and 13, from the output of the m-bit shift register 8, comes the code vector Y _i .

- состояние "правильное декодирование";
или X_i ≠ Y_i,

- состояние "ошибка декодирования",
где X_i произвольный эталонный кодовый вектор из множества векторов X₁, X₂,...X_n, то на выходе одного из m-разрядных сумматоров по модулю два (12,.. 13) будет сигнал "0", а на выходах остальных m-разрядных сумматоров по модулю два (12,...13) будет сигнал "1". В результате поступления сигнала "0" с выхода одного из m-разрядных сумматоров по модулю два (12,...13) на один из входов элемента И 14 и поступления сигналов "1" с выходов остальных m-разрядных сумматоров по модулю два (12,...13) на остальные входы элемента И 14, на выходе элемента И 14 образуется сигнал "0" (количество входов элемента И 14 равно количеству m- разрядных сумматоров по модулю два и равно количеству эталонных кодовых векторов n).If the code vector Y _i satisfies the conditions (case I):
X _i = Y _i ,

- state "correct decoding";
or X _i ≠ Y _i ,

- state "decoding error",
where X _{i is} an arbitrary reference code vector from the set of vectors X ₁ , X ₂ , ... X _n , then at the output of one of the m-bit adders modulo two (12, .. 13) there will be a signal "0", and at the outputs the remaining m-bit adders modulo two (12, ... 13) will be the signal "1". As a result of the signal “0” from the output of one of the m-bit adders modulo two (12, ... 13) to one of the inputs of the element And 14 and the input of signals “1” from the outputs of the remaining m-bit adders modulo two ( 12, ... 13) to the other inputs of the element And 14, the signal "0" is generated at the output of the element And 14 (the number of inputs of the And 14 element is equal to the number of m-bit adders modulo two and equal to the number of reference code vectors n).

. Поэтому на приемной стороне системы случай I воспринимается как сигнал правильной передачи и приема кодового вектора X_i. С выхода элемента И 14 сигнал "0" поступает на вход 2 процессора 7. В результате этого кодовый вектор Y_i считывается с выхода 2 процессора 7 в устройство обработки (не показано), где из него выделяется k информационных разрядов (избыточные m-k разрядов при этом отбрасываются). Сформированное, таким образом из кодового вектора Y_i, k-разрядное информационное сообщение A'_j поступает далее на обработку.The appearance of the signal "0" at the output of AND element 14 means a situation: "correct decoding" or "decoding error." On the receiving side of the state system: “correct decoding” or “decoding error” (case I) are not distinguishable. The "decoding error" state at the receiving side of the system is not detected (any CK _i has a certain probability of decoding error

. Therefore, on the receiving side of the system, case I is perceived as a signal of the correct transmission and reception of the code vector X _i . From the output of element And 14, the signal "0" is fed to input 2 of processor 7. As a result, code vector Y _{i is} read from output 2 of processor 7 to a processing device (not shown), where k information bits are allocated from it (excess mk bits discarded). Thus formed from the code vector Y _i , the k-bit information message A ′ _j is further processed.

 The signal "0" (case I) from the output of the element And 14 is fed to the input of the return channel 15 of digital information, the output of which the signal "0" is fed to one of the two inputs of the element And 16, the other input of which receives a clock pulse (having the value " 1 ") from the output of the delay element 17, the input of which receives a signal from the clock generator 18.

In FIG. 2 the following signals are indicated:
a - signals "0" or "1" from the output of the element And 14;
b - clock pulses (having the value "1") from the generator 18 clock pulses. The time interval Tn between clock pulses is equal to the transmission time of the code vector X _i on the forward channel 4, plus the processing time of the digital information on the receiving side of the system, plus the transmission time on the reverse channel 15.

From the output of element And 16, the signal "0" is fed to the input 2 of the first processor 3. From the output 2 of the first processor 3, a control signal is supplied to input 2 of the first buffer register 1, as a result of which the next discrete signal is output from the output of the first buffer register 1 information A _{j + 1} .

- состояние "отказ от декодирования",
то на выходе всех m-разрядных сумматоров по модулю два (12,...13) будет сигнал "1". В результате поступления сигналов "1" с выходов всех m-разрядных сумматоров по модулю два (12,...13) на все входы элемента И 14, на выходе элемента И 14 образуется сигнал "1".If the condition vector (case II) is satisfied for the code vector Y _i :
X _i ≠ Y _i ,

- state "reject decoding",
then the output of all m-bit adders modulo two (12, ... 13) will be the signal "1". As a result of the arrival of signals "1" from the outputs of all m-bit adders modulo two (12, ... 13) to all inputs of the element And 14, the signal "1" is formed at the output of the element And 14.

. Если с выхода элемента И 14 поступает сигнал "1" на вход 2 процессора 7, то кодовый вектор Y_i не считывается (так как на приемной стороне случай II обнаруживается как состояние "отказ от декодирования"). Сигнал "1" с выхода элемента И 14 поступает одновременно на вход обратного канала 15 передачи цифровой информации, с выхода которого сигнал "1" поступает на один из двух входов элемента И 16, на другой вход которого поступает тактовый импульс с выхода элемента задержки 17, на вход которого поступает сигнал с генератора 18 тактовых импульсов. С выхода элемента И 16 сигнал "1", в момент поступления тактового импульса (имеющего значение "1") поступает на вход 2 первого процессора 3. В этом случае, с выхода 1 первого процессора 3 на вход прямого канала 4 передачи цифровой информации, повторно поступает кодовый вектор X_i (ранее запомненный в первом процессоре 3), с целью обеспечения достоверной передачи информации в системе. Одновременно (в случае II) с выхода 2 первого процессора 3 поступает управляющий сигнал на вход 2 первого буферного регистра 1, в результате чего с выхода первого буферного регистра 1 на вход кодера 2 не поступает следующая дискретная информация A_j+1.The appearance of the signal "1" at the output of the element And 14 means the situation "refusal of decoding." On the receiving side of the system, a “decoding rejection” situation is detected during the verification of the condition X _i ≠ Y _i ,

. If the output of element And 14 receives the signal "1" to input 2 of the processor 7, then the code vector Y _{i is} not read (since case II is detected on the receiving side as a "decoding rejection" state). The signal "1" from the output of the element And 14 is fed simultaneously to the input of the return channel 15 for transmitting digital information, the output of which the signal "1" is fed to one of the two inputs of the element And 16, the other input of which receives a clock pulse from the output of the delay element 17, the input of which receives a signal from the generator 18 clock pulses. From the output of element And 16, the signal "1", at the time of receipt of the clock pulse (having the value "1"), is fed to input 2 of the first processor 3. In this case, from the output 1 of the first processor 3 to the input of the direct channel 4 for transmitting digital information, repeatedly comes the code vector X _i (previously stored in the first processor 3), in order to ensure reliable transmission of information in the system. At the same time (in case II), output 2 of the first processor 3 receives a control signal at input 2 of the first buffer register 1, as a result of which the output of the first buffer register 1 does not receive the following discrete information A _{j + 1} .

 Next, the cycle of work is repeated.

 The application of the proposed system allows to increase the reliability of the transmission of digital information over communication channels subject to pulsed and other interference while ensuring high speed information transfer.

Claims (1)

 An adaptive system for transmitting and receiving discrete information containing a buffer register on the transmitting side, an adder modulo two on the receiving side, the first input of which is connected to the output of the shift register, as well as the first and second elements And, the control unit containing an additional buffer register, a clock generator and a delay element, characterized in that an encoder and a processor are introduced on the transmitting side, and a buffer register, a decoder, a processor, two additional shift registers and additional are introduced on the receiving side There are two modulo adders, the buffer register, encoder and processor on the transmitting side being connected in series, from the first output of the processor on the transmitting side, the code vector is fed to the input of the direct channel for transmitting digital information, from the output of which goes to the input of the buffer register of the receiving side, on which the buffer register, decoder and processor are connected in series, from the first output of the processor on the receiving side, the code vector is fed to the input of the shift register, the additional buffer register is by means of additional shift registers it is connected modulo two to the corresponding adder inputs, the modulo two other input of the additional adder is connected to the output of the shift register from the second processor output on the receiving side, the correctly received code vector is read, the modulo two outputs of the adders are connected to the inputs of the first element And, from the output of which the signal goes to the second input of the processor and to the input of the return channel for transmitting digital information, from the output of which the signal goes to one input of the second element And, whose output through the processor on the transmitting side is connected to the second input of the buffer register, the first input of which receives a control signal, and the output of the pulse generator through the delay element is connected to another input of the second element I.

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